SVP: scan-line video processor

Hidetoshi Onuma, Yuji Yaguchi, Hiroshi Miyaguchi, Tsuyoshi Akiyama, Katsumi Kajiyama, Kenya Adachi, Atsushi Kikuchi, Takao Kojima, Takashi Narumi

Research output: Contribution to conferencePaper

Abstract

SVP achieved fast processing rate exceeding standard DSPs by integrating 1024 PEs (Processing Elements). 50MHz operation in each PEs in the SIMD (Single Instruction Multiple Data) scheme is realized on two stage pipelines in IG (Instruction Generator) and five stage pipelines in PE CORE. With the realization of 20ns DRAM cycle in each PEs and the system clock generated through PLL, SVP enables full-spec-EDTV2 (the second generation Enhanced Definition Television in Japan).

Original languageEnglish
Pages196-200
Number of pages5
Publication statusPublished - 1995 Dec 1
Externally publishedYes
EventProceedings of the 1995 International Symposium on VLSI Technology, Systems, and Applications - Taipei, Taiwan
Duration: 1995 May 311995 Jun 2

Other

OtherProceedings of the 1995 International Symposium on VLSI Technology, Systems, and Applications
CityTaipei, Taiwan
Period95/5/3195/6/2

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering

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  • Cite this

    Onuma, H., Yaguchi, Y., Miyaguchi, H., Akiyama, T., Kajiyama, K., Adachi, K., Kikuchi, A., Kojima, T., & Narumi, T. (1995). SVP: scan-line video processor. 196-200. Paper presented at Proceedings of the 1995 International Symposium on VLSI Technology, Systems, and Applications, Taipei, Taiwan, .