Abstract
SVP achieved fast processing rate exceeding standard DSPs by integrating 1024 PEs (Processing Elements). 50MHz operation in each PEs in the SIMD (Single Instruction Multiple Data) scheme is realized on two stage pipelines in IG (Instruction Generator) and five stage pipelines in PE CORE. With the realization of 20ns DRAM cycle in each PEs and the system clock generated through PLL, SVP enables full-spec-EDTV2 (the second generation Enhanced Definition Television in Japan).
Original language | English |
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Pages | 196-200 |
Number of pages | 5 |
Publication status | Published - 1995 Dec 1 |
Externally published | Yes |
Event | Proceedings of the 1995 International Symposium on VLSI Technology, Systems, and Applications - Taipei, Taiwan Duration: 1995 May 31 → 1995 Jun 2 |
Other
Other | Proceedings of the 1995 International Symposium on VLSI Technology, Systems, and Applications |
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City | Taipei, Taiwan |
Period | 95/5/31 → 95/6/2 |
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Condensed Matter Physics
- Electrical and Electronic Engineering