SVP: scan-line video processor

Hidetoshi Onuma; Yuji Yaguchi; Hiroshi Miyaguchi; Tsuyoshi Akiyama; Katsumi Kajiyama; Kenya Adachi; Atsushi Kikuchi; Takao Kojima; Takashi Narumi

SVP: scan-line video processor

Hidetoshi Onuma, Yuji Yaguchi, Hiroshi Miyaguchi, Tsuyoshi Akiyama, Katsumi Kajiyama, Kenya Adachi, Atsushi Kikuchi, Takao Kojima, Takashi Narumi

Research output: Contribution to conference › Paper › peer-review

1 Citation (Scopus)

Abstract

SVP achieved fast processing rate exceeding standard DSPs by integrating 1024 PEs (Processing Elements). 50MHz operation in each PEs in the SIMD (Single Instruction Multiple Data) scheme is realized on two stage pipelines in IG (Instruction Generator) and five stage pipelines in PE CORE. With the realization of 20ns DRAM cycle in each PEs and the system clock generated through PLL, SVP enables full-spec-EDTV2 (the second generation Enhanced Definition Television in Japan).

Original language	English
Pages	196-200
Number of pages	5
Publication status	Published - 1995 Dec 1
Externally published	Yes
Event	Proceedings of the 1995 International Symposium on VLSI Technology, Systems, and Applications - Taipei, Taiwan Duration: 1995 May 31 → 1995 Jun 2

Other

Other	Proceedings of the 1995 International Symposium on VLSI Technology, Systems, and Applications
City	Taipei, Taiwan
Period	95/5/31 → 95/6/2

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Electrical and Electronic Engineering

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SVP : scan-line video processor. / Onuma, Hidetoshi; Yaguchi, Yuji; Miyaguchi, Hiroshi; Akiyama, Tsuyoshi; Kajiyama, Katsumi; Adachi, Kenya; Kikuchi, Atsushi; Kojima, Takao; Narumi, Takashi.

1995. 196-200 Paper presented at Proceedings of the 1995 International Symposium on VLSI Technology, Systems, and Applications, Taipei, Taiwan, .

Research output: Contribution to conference › Paper › peer-review

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abstract = "SVP achieved fast processing rate exceeding standard DSPs by integrating 1024 PEs (Processing Elements). 50MHz operation in each PEs in the SIMD (Single Instruction Multiple Data) scheme is realized on two stage pipelines in IG (Instruction Generator) and five stage pipelines in PE CORE. With the realization of 20ns DRAM cycle in each PEs and the system clock generated through PLL, SVP enables full-spec-EDTV2 (the second generation Enhanced Definition Television in Japan).",

author = "Hidetoshi Onuma and Yuji Yaguchi and Hiroshi Miyaguchi and Tsuyoshi Akiyama and Katsumi Kajiyama and Kenya Adachi and Atsushi Kikuchi and Takao Kojima and Takashi Narumi",

year = "1995",

month = dec,

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language = "English",

pages = "196--200",

note = "Proceedings of the 1995 International Symposium on VLSI Technology, Systems, and Applications ; Conference date: 31-05-1995 Through 02-06-1995",

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T2 - Proceedings of the 1995 International Symposium on VLSI Technology, Systems, and Applications

AU - Onuma, Hidetoshi

AU - Yaguchi, Yuji

AU - Miyaguchi, Hiroshi

AU - Akiyama, Tsuyoshi

AU - Kajiyama, Katsumi

AU - Adachi, Kenya

AU - Kikuchi, Atsushi

AU - Kojima, Takao

AU - Narumi, Takashi

PY - 1995/12/1

Y1 - 1995/12/1

N2 - SVP achieved fast processing rate exceeding standard DSPs by integrating 1024 PEs (Processing Elements). 50MHz operation in each PEs in the SIMD (Single Instruction Multiple Data) scheme is realized on two stage pipelines in IG (Instruction Generator) and five stage pipelines in PE CORE. With the realization of 20ns DRAM cycle in each PEs and the system clock generated through PLL, SVP enables full-spec-EDTV2 (the second generation Enhanced Definition Television in Japan).

AB - SVP achieved fast processing rate exceeding standard DSPs by integrating 1024 PEs (Processing Elements). 50MHz operation in each PEs in the SIMD (Single Instruction Multiple Data) scheme is realized on two stage pipelines in IG (Instruction Generator) and five stage pipelines in PE CORE. With the realization of 20ns DRAM cycle in each PEs and the system clock generated through PLL, SVP enables full-spec-EDTV2 (the second generation Enhanced Definition Television in Japan).

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Y2 - 31 May 1995 through 2 June 1995

ER -

SVP: scan-line video processor

Abstract

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ASJC Scopus subject areas

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