Suppression of anomalous threshold voltage increase with area scaling for Mg- or La-incorporated high-k/metal gate nMISFETs in deeply scaled region

T. Morooka, M. Sato, T. Matsuki, T. Suzuki, K. Shiraishi, A. Uedono, S. Miyazaki, K. Ohmori, K. Yamada, T. Nabatame, T. Chikyow, J. Yugami, K. Ikeda, Y. Ohji

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Citations (Scopus)

Abstract

Anomalous threshold voltage increase with area scaling of Mg- or La-incorporated high-k gate dielectrics has great impact on scaled devices. This paper reveals that much amount of Mg or La capping effects for Vt reduction was disappeared with the increase of electron mobility in narrow channel nMISFETs. This phenomenon is explained with absorption of Mg and La into STI from bulk high-k layer. The key to suppress the area scaling dependence is pilling Mg or La atoms up near high-k/IFL interface which enable us increase of stable capping effect. Combination of processing for high-k gate dielectrics and device structure with the high-k dielectrics under offset spacers was found to effectively suppress the Vt increase at the 100 nm channel width. As a conclusion, the large capping effect for Vt reduction over 400 mV is achieved in scaled devices using this technique.

Original languageEnglish
Title of host publication2010 Symposium on VLSI Technology, VLSIT 2010
Pages33-34
Number of pages2
DOIs
Publication statusPublished - 2010
Externally publishedYes
Event2010 Symposium on VLSI Technology, VLSIT 2010 - Honolulu, HI, United States
Duration: 2010 Jun 152010 Jun 17

Publication series

NameDigest of Technical Papers - Symposium on VLSI Technology
ISSN (Print)0743-1562

Other

Other2010 Symposium on VLSI Technology, VLSIT 2010
Country/TerritoryUnited States
CityHonolulu, HI
Period10/6/1510/6/17

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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