Super-dynamic flip-flop circuit for broadband applications up to 24 Gbit/s utilizing production-level 0.2-μm GaAs MESFETs

Taiichi Otsuji, Mikio Yoneyama, Koichi Murata, Eiichi Sano

Research output: Contribution to conferencePaper

19 Citations (Scopus)

Abstract

This paper describes a novel dynamic flip-flop (FF) circuit that can operate 30% faster than conventional clocked inverter-type FFs. A new wide-band clock buffer is introduced to cover the FF operation range. An 8- to 24-Gbit/s decision circuit and a 9- to 26-GHz 1/2 frequency divider were developed using production-level 0.2-μm GaAs MESFET technology.

Original languageEnglish
Pages145-148
Number of pages4
Publication statusPublished - 1996 Dec 1
Externally publishedYes
EventProceedings of the 1996 18th Annual IEEE Gallium Arsenide Integrated Circuit Symposium - Orlando, FL, USA
Duration: 1996 Nov 31996 Nov 6

Other

OtherProceedings of the 1996 18th Annual IEEE Gallium Arsenide Integrated Circuit Symposium
CityOrlando, FL, USA
Period96/11/396/11/6

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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  • Cite this

    Otsuji, T., Yoneyama, M., Murata, K., & Sano, E. (1996). Super-dynamic flip-flop circuit for broadband applications up to 24 Gbit/s utilizing production-level 0.2-μm GaAs MESFETs. 145-148. Paper presented at Proceedings of the 1996 18th Annual IEEE Gallium Arsenide Integrated Circuit Symposium, Orlando, FL, USA, .