Sub-10 nm multi-nano-pillar type vertical MOSFET

Tetsuo Endoh, Koji Sakui, Yukio Yasuda

Research output: Contribution to journalArticlepeer-review

13 Citations (Scopus)

Abstract

The excellent performance of the 10 nm gate Multi-Nano- Pillar type (M-) Vertical MOSFET has been numerically shown for the first time. It is made clear that the M-Vertical MOSFET, in comparison with the conventional Single Pillar type (S-) Vertical MOSFET, has achieved an increased driving current by more than 2 times, a nearly ideal S-factor, and a suppressed cutoff-leakage current by less than 1/60 by suppressing both the short channel effect and the DIBL effect. Moreover, mechanisms of these improvements of the M-Vertical MOSFET are made clear. From all of the above, it is shown that the M-Vertical MOSFET is a key device candidate for future high speed and low power LSI's in the sub-10 nm generation.

Original languageEnglish
Pages (from-to)557-562
Number of pages6
JournalIEICE Transactions on Electronics
VolumeE93-C
Issue number5
DOIs
Publication statusPublished - 2010 Jan 1

Keywords

  • 3D structured device
  • LSI
  • MOSFET
  • Vertical MOSFET

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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