Study of the DC performance of fabricated magnetic tunnel junction integrated on back-end metal line of CMOS circuits

Fumitaka Iga, Masashi Kamiyanagi, Shoji Ikeda, Katsuya Miur, Jun Hayakawa, Haruhiro Hasegawa, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh

Research output: Contribution to journalArticle

Abstract

In this paper, we have succeeded in the fabrication of high performance Magnetic Tunnel Junction (MTJ) which is integrated in CMOS circuit with 4-Metal/1-poly Gate 0.14 μm CMOS process. We have measured the DC characteristics of the MTJ that is fabricated on via metal of 3rd layer metal line. This MTJ of 60 × 180 nm2 achieves a large change in resistance of 3.52 kΩ (anti-parallel) with TMR ratio of 151% at room temperature, which is large enough for sensing scheme of standard CMOS logic. Furthermore, the write current is 320 μA that can be driven by a standard MOS transistor. As the results, it is shown that the DC performance of our fabricated MTJ integrated in CMOS circuits is very good for our novel spin logic (MTJ-based logic) device.

Original languageEnglish
Pages (from-to)608-613
Number of pages6
JournalIEICE Transactions on Electronics
VolumeE93-C
Issue number5
DOIs
Publication statusPublished - 2010 Jan 1

Keywords

  • Current-induced magnetization switching
  • Magnetic tunnel junction (MTJ)
  • Magnetoresistive RAM (MRAM)
  • Spin-transfer torque RAM (STT-RAM)
  • Tunnel magnetoresistance (TMR)

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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