Study of self-heating in Si nano structure for floating body-surround gate transistor with high-k dielectric films

In this study, to overcome temperature-related problems of floating body-surround gate transistors with high-k materials, we have numerically investigated the temperature distribution in n-type silicon (Si) nanowires, in relation to the self-heating effect at steady state, by using a three-dimensional (3-D) device simulator. The dependences of temperature distribution in the Si nanowire on impurity concentration and cross sectional area were analyzed. First, it was found that the maximum temperature in the Si nanowire increases with increasing impurity concentration, and the increasing maximum temperature leads to a larger shift of the position of the maximum temperature from the center. Next, it was also found that the temperature distribution is independent of the cross sectional area of the Si nanowire. Finally, it was clarified that the asymmetric temperature distribution in the Si nanowire is caused by the Seebeck effect. This study shows useful results for future nano-scale silicon-metal oxide semiconductor (Si-MOS) device design to suppress the self-heating effect.