TY - GEN
T1 - Structural reliability design of plastic packages using Cu-alloy lead-frames
AU - Miura, H.
PY - 2003/1/1
Y1 - 2003/1/1
N2 - The residual stress in silicon chips encapsulated in plastic packages using Cu-alloy frames was measured using stress sensing chips by varying the combination of structure and material of metallic lead-frames and molding resin because the mechanical reliability such as cracking of silicon chips and the shift of the electronic performance of LSI strongly depends on the stress. Since the adhesion condition between a silicon chip and the Cu-alloy frame was unstable due to the large mismatch in thermal expansion coefficient between them, the residual stress after encapsulation varied from tensile stress to high compressive stress depending on the combination of the packaging materials such as die-bonding paste and molding resin. It was found that the residual stress can be controlled and minimized by using the chip-on-lead (COL) type package because the dielectric film between the Cu-alloy frame and a silicon chip acts as a stress relaxation layer.
AB - The residual stress in silicon chips encapsulated in plastic packages using Cu-alloy frames was measured using stress sensing chips by varying the combination of structure and material of metallic lead-frames and molding resin because the mechanical reliability such as cracking of silicon chips and the shift of the electronic performance of LSI strongly depends on the stress. Since the adhesion condition between a silicon chip and the Cu-alloy frame was unstable due to the large mismatch in thermal expansion coefficient between them, the residual stress after encapsulation varied from tensile stress to high compressive stress depending on the combination of the packaging materials such as die-bonding paste and molding resin. It was found that the residual stress can be controlled and minimized by using the chip-on-lead (COL) type package because the dielectric film between the Cu-alloy frame and a silicon chip acts as a stress relaxation layer.
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U2 - 10.1109/EPTC.2003.1271625
DO - 10.1109/EPTC.2003.1271625
M3 - Conference contribution
AN - SCOPUS:84857642656
T3 - Proceedings of 5th Electronics Packaging Technology Conference, EPTC 2003
SP - 785
EP - 790
BT - Proceedings of 5th Electronics Packaging Technology Conference, EPTC 2003
A2 - Iyer, Mahadevan K.
A2 - Mui, Yew Cheong
A2 - Toh, Kok Chuan
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 5th Electronics Packaging Technology Conference, EPTC 2003
Y2 - 10 December 2003 through 12 December 2003
ER -