Structural design of three-dimensionally stacked silicon chips mounted by flip chip technology for minimizing their residual stress

Nobuki Ueta, Takuya Sasaki, Hideo Miura

Research output: Contribution to journalArticle

Abstract

The residual stress in LSI chips mounted in synchronous stacked bump structures such as stacked memory structures varies drastically depending on their bump joint structures. It sometimes reaches a few hundred MPa and deteriorates their functions and the reliability of products. Thus, a new bump joint structure is proposed for minimizing the residual stress considering the relative positions between bumps and vias using a finite element analysis. The amplitude of the residual stress in each stacked chip in the optimum stacked structure can be decreased to less than 30 MPa and the difference of the residual stress between the stacked chips to nearly 0 MPa. The alternative alignment structure between bumps and vias is effective for minimizing the local residual stress in a chip. Introducing a stress-relaxation layer under the bump using a material with a low elastic modulus is also effective for minimizing the local residual stress. Therefore, it is important to optimize the assembly structure of the three-dimensionally stacked LSI chips in order to minimize the residual stress.

Original languageEnglish
Pages (from-to)519-525
Number of pages7
JournalJournal of Japan Institute of Electronics Packaging
Volume12
Issue number6
DOIs
Publication statusPublished - 2009 Sep 1

Keywords

  • Flip Chip Structure
  • Reliability
  • Residual Stress
  • Structural Design
  • Three-dimensionally Stacked Structure

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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