Strain enhanced FUSI/HfSiON technology with optimized CMOS process window

A. Veloso; P. Verheyen; R. Vos; S. Brus; S. Ito; R. Mitsuhashi; V. Paraschiv; X. Shi; B. Onsia; S. Arnauts; R. Loo; A. Lauwers; T. Conard; J. F. De Marneffe; D. Goossens; D. Baute; S. Locorotondo; T. Chiarella; C. Kerner; C. Vrancken; S. Mertens; B. J. O'Sullivan; H. Y. Yu; S. Z. Chang; Masaaki Niwa; J. A. Kittl; P. P. Absil; M. Jurczak; T. Hoffmann; S. Biesemans

doi:10.1109/VLSIT.2007.4339692

Strain enhanced FUSI/HfSiON technology with optimized CMOS process window

A. Veloso, P. Verheyen, R. Vos, S. Brus, S. Ito, R. Mitsuhashi, V. Paraschiv, X. Shi, B. Onsia, S. Arnauts, R. Loo, A. Lauwers, T. Conard, J. F. De Marneffe, D. Goossens, D. Baute, S. Locorotondo, T. Chiarella, C. Kerner, C. VranckenS. Mertens, B. J. O'Sullivan, H. Y. Yu, S. Z. Chang, Masaaki Niwa, J. A. Kittl, P. P. Absil, M. Jurczak, T. Hoffmann, S. Biesemans

Research output: Contribution to journal › Conference article

2 Citations (Scopus)

Abstract

We report, for the first time, a comprehensive study on the compatibility of state-of-the-art performance boosters with FUSI/HfSiON technology, resulting in record high-V _T NMOS and PMOS devices with 725/370 μA/μm (at V _DD =1.1V, Ioff=20pA/μm and Jg=100/1 mA/cm ² ). We demonstrate that adding embedded Si _0.75 Ge _0.25 in S/D regions resulted in 45% performance improvement over the FUSI/HfSiON reference, and that the V _T distribution is tight and comparable to baseline. For process simplicity purposes, dual phase Ni-FUSI (NiSi NMOS; Ni ₃₁ Si ₁₂ or Ni ₂ Si PMOS) is formed simultaneously in our integration scheme, each phase having its own process window (PW). In this work, we successfully maximized the common CMOS PW by 2 crucial process improvements: - shining up the NMOS RTP1 temperature (T) PW by nitrogen implantation in NMOS poly gates prior to Ni deposition for FUSI; - extending the PMOS PW to lower RTP1 temperatures by improved surface preparation after novel poly etch-back process.

Original language	English
Article number	4339692
Pages (from-to)	200-201
Number of pages	2
Journal	Digest of Technical Papers - Symposium on VLSI Technology
DOIs	https://doi.org/10.1109/VLSIT.2007.4339692
Publication status	Published - 2007 Dec 1
Externally published	Yes
Event	2007 Symposium on VLSI Technology, VLSIT 2007 - Kyoto, Japan Duration: 2007 Jun 12 → 2007 Jun 14

ASJC Scopus subject areas

Electrical and Electronic Engineering

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Veloso, A., Verheyen, P., Vos, R., Brus, S., Ito, S., Mitsuhashi, R., Paraschiv, V., Shi, X., Onsia, B., Arnauts, S., Loo, R., Lauwers, A., Conard, T., De Marneffe, J. F., Goossens, D., Baute, D., Locorotondo, S., Chiarella, T., Kerner, C., ... Biesemans, S. (2007). Strain enhanced FUSI/HfSiON technology with optimized CMOS process window. Digest of Technical Papers - Symposium on VLSI Technology, 200-201. [4339692]. https://doi.org/10.1109/VLSIT.2007.4339692

Strain enhanced FUSI/HfSiON technology with optimized CMOS process window. / Veloso, A.; Verheyen, P.; Vos, R.; Brus, S.; Ito, S.; Mitsuhashi, R.; Paraschiv, V.; Shi, X.; Onsia, B.; Arnauts, S.; Loo, R.; Lauwers, A.; Conard, T.; De Marneffe, J. F.; Goossens, D.; Baute, D.; Locorotondo, S.; Chiarella, T.; Kerner, C.; Vrancken, C.; Mertens, S.; O'Sullivan, B. J.; Yu, H. Y.; Chang, S. Z.; Niwa, Masaaki; Kittl, J. A.; Absil, P. P.; Jurczak, M.; Hoffmann, T.; Biesemans, S.

In: Digest of Technical Papers - Symposium on VLSI Technology, 01.12.2007, p. 200-201.

Research output: Contribution to journal › Conference article

Veloso, A, Verheyen, P, Vos, R, Brus, S, Ito, S, Mitsuhashi, R, Paraschiv, V, Shi, X, Onsia, B, Arnauts, S, Loo, R, Lauwers, A, Conard, T, De Marneffe, JF, Goossens, D, Baute, D, Locorotondo, S, Chiarella, T, Kerner, C, Vrancken, C, Mertens, S, O'Sullivan, BJ, Yu, HY, Chang, SZ, Niwa, M, Kittl, JA, Absil, PP, Jurczak, M, Hoffmann, T & Biesemans, S 2007, 'Strain enhanced FUSI/HfSiON technology with optimized CMOS process window', Digest of Technical Papers - Symposium on VLSI Technology, pp. 200-201. https://doi.org/10.1109/VLSIT.2007.4339692

Veloso, A. ; Verheyen, P. ; Vos, R. ; Brus, S. ; Ito, S. ; Mitsuhashi, R. ; Paraschiv, V. ; Shi, X. ; Onsia, B. ; Arnauts, S. ; Loo, R. ; Lauwers, A. ; Conard, T. ; De Marneffe, J. F. ; Goossens, D. ; Baute, D. ; Locorotondo, S. ; Chiarella, T. ; Kerner, C. ; Vrancken, C. ; Mertens, S. ; O'Sullivan, B. J. ; Yu, H. Y. ; Chang, S. Z. ; Niwa, Masaaki ; Kittl, J. A. ; Absil, P. P. ; Jurczak, M. ; Hoffmann, T. ; Biesemans, S. / Strain enhanced FUSI/HfSiON technology with optimized CMOS process window. In: Digest of Technical Papers - Symposium on VLSI Technology. 2007 ; pp. 200-201.

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title = "Strain enhanced FUSI/HfSiON technology with optimized CMOS process window",

abstract = " We report, for the first time, a comprehensive study on the compatibility of state-of-the-art performance boosters with FUSI/HfSiON technology, resulting in record high-V T NMOS and PMOS devices with 725/370 μA/μm (at V DD =1.1V, Ioff=20pA/μm and Jg=100/1 mA/cm 2 ). We demonstrate that adding embedded Si 0.75 Ge 0.25 in S/D regions resulted in 45% performance improvement over the FUSI/HfSiON reference, and that the V T distribution is tight and comparable to baseline. For process simplicity purposes, dual phase Ni-FUSI (NiSi NMOS; Ni 31 Si 12 or Ni 2 Si PMOS) is formed simultaneously in our integration scheme, each phase having its own process window (PW). In this work, we successfully maximized the common CMOS PW by 2 crucial process improvements: - shining up the NMOS RTP1 temperature (T) PW by nitrogen implantation in NMOS poly gates prior to Ni deposition for FUSI; - extending the PMOS PW to lower RTP1 temperatures by improved surface preparation after novel poly etch-back process. ",

author = "A. Veloso and P. Verheyen and R. Vos and S. Brus and S. Ito and R. Mitsuhashi and V. Paraschiv and X. Shi and B. Onsia and S. Arnauts and R. Loo and A. Lauwers and T. Conard and {De Marneffe}, {J. F.} and D. Goossens and D. Baute and S. Locorotondo and T. Chiarella and C. Kerner and C. Vrancken and S. Mertens and O'Sullivan, {B. J.} and Yu, {H. Y.} and Chang, {S. Z.} and Masaaki Niwa and Kittl, {J. A.} and Absil, {P. P.} and M. Jurczak and T. Hoffmann and S. Biesemans",

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T1 - Strain enhanced FUSI/HfSiON technology with optimized CMOS process window

AU - Veloso, A.

AU - Verheyen, P.

AU - Vos, R.

AU - Brus, S.

AU - Ito, S.

AU - Mitsuhashi, R.

AU - Paraschiv, V.

AU - Shi, X.

AU - Onsia, B.

AU - Arnauts, S.

AU - Loo, R.

AU - Lauwers, A.

AU - Conard, T.

AU - De Marneffe, J. F.

AU - Goossens, D.

AU - Baute, D.

AU - Locorotondo, S.

AU - Chiarella, T.

AU - Kerner, C.

AU - Vrancken, C.

AU - Mertens, S.

AU - O'Sullivan, B. J.

AU - Yu, H. Y.

AU - Chang, S. Z.

AU - Niwa, Masaaki

AU - Kittl, J. A.

AU - Absil, P. P.

AU - Jurczak, M.

AU - Hoffmann, T.

AU - Biesemans, S.

PY - 2007/12/1

Y1 - 2007/12/1

N2 - We report, for the first time, a comprehensive study on the compatibility of state-of-the-art performance boosters with FUSI/HfSiON technology, resulting in record high-V T NMOS and PMOS devices with 725/370 μA/μm (at V DD =1.1V, Ioff=20pA/μm and Jg=100/1 mA/cm 2 ). We demonstrate that adding embedded Si 0.75 Ge 0.25 in S/D regions resulted in 45% performance improvement over the FUSI/HfSiON reference, and that the V T distribution is tight and comparable to baseline. For process simplicity purposes, dual phase Ni-FUSI (NiSi NMOS; Ni 31 Si 12 or Ni 2 Si PMOS) is formed simultaneously in our integration scheme, each phase having its own process window (PW). In this work, we successfully maximized the common CMOS PW by 2 crucial process improvements: - shining up the NMOS RTP1 temperature (T) PW by nitrogen implantation in NMOS poly gates prior to Ni deposition for FUSI; - extending the PMOS PW to lower RTP1 temperatures by improved surface preparation after novel poly etch-back process.

AB - We report, for the first time, a comprehensive study on the compatibility of state-of-the-art performance boosters with FUSI/HfSiON technology, resulting in record high-V T NMOS and PMOS devices with 725/370 μA/μm (at V DD =1.1V, Ioff=20pA/μm and Jg=100/1 mA/cm 2 ). We demonstrate that adding embedded Si 0.75 Ge 0.25 in S/D regions resulted in 45% performance improvement over the FUSI/HfSiON reference, and that the V T distribution is tight and comparable to baseline. For process simplicity purposes, dual phase Ni-FUSI (NiSi NMOS; Ni 31 Si 12 or Ni 2 Si PMOS) is formed simultaneously in our integration scheme, each phase having its own process window (PW). In this work, we successfully maximized the common CMOS PW by 2 crucial process improvements: - shining up the NMOS RTP1 temperature (T) PW by nitrogen implantation in NMOS poly gates prior to Ni deposition for FUSI; - extending the PMOS PW to lower RTP1 temperatures by improved surface preparation after novel poly etch-back process.

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JO - Digest of Technical Papers - Symposium on VLSI Technology

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