TY - JOUR
T1 - Strain enhanced FUSI/HfSiON technology with optimized CMOS process window
AU - Veloso, A.
AU - Verheyen, P.
AU - Vos, R.
AU - Brus, S.
AU - Ito, S.
AU - Mitsuhashi, R.
AU - Paraschiv, V.
AU - Shi, X.
AU - Onsia, B.
AU - Arnauts, S.
AU - Loo, R.
AU - Lauwers, A.
AU - Conard, T.
AU - De Marneffe, J. F.
AU - Goossens, D.
AU - Baute, D.
AU - Locorotondo, S.
AU - Chiarella, T.
AU - Kerner, C.
AU - Vrancken, C.
AU - Mertens, S.
AU - O'Sullivan, B. J.
AU - Yu, H. Y.
AU - Chang, S. Z.
AU - Niwa, M.
AU - Kittl, J. A.
AU - Absil, P. P.
AU - Jurczak, M.
AU - Hoffmann, T.
AU - Biesemans, S.
PY - 2007
Y1 - 2007
N2 - We report, for the first time, a comprehensive study on the compatibility of state-of-the-art performance boosters with FUSI/HfSiON technology, resulting in record high-VT NMOS and PMOS devices with 725/370 μA/μm (at VDD=1.1V, Ioff=20pA/μm and Jg=100/1 mA/cm2). We demonstrate that adding embedded Si0.75Ge0.25 in S/D regions resulted in 45% performance improvement over the FUSI/HfSiON reference, and that the VT distribution is tight and comparable to baseline. For process simplicity purposes, dual phase Ni-FUSI (NiSi NMOS; Ni 31Si12 or Ni2Si PMOS) is formed simultaneously in our integration scheme, each phase having its own process window (PW). In this work, we successfully maximized the common CMOS PW by 2 crucial process improvements: - shining up the NMOS RTP1 temperature (T) PW by nitrogen implantation in NMOS poly gates prior to Ni deposition for FUSI; - extending the PMOS PW to lower RTP1 temperatures by improved surface preparation after novel poly etch-back process.
AB - We report, for the first time, a comprehensive study on the compatibility of state-of-the-art performance boosters with FUSI/HfSiON technology, resulting in record high-VT NMOS and PMOS devices with 725/370 μA/μm (at VDD=1.1V, Ioff=20pA/μm and Jg=100/1 mA/cm2). We demonstrate that adding embedded Si0.75Ge0.25 in S/D regions resulted in 45% performance improvement over the FUSI/HfSiON reference, and that the VT distribution is tight and comparable to baseline. For process simplicity purposes, dual phase Ni-FUSI (NiSi NMOS; Ni 31Si12 or Ni2Si PMOS) is formed simultaneously in our integration scheme, each phase having its own process window (PW). In this work, we successfully maximized the common CMOS PW by 2 crucial process improvements: - shining up the NMOS RTP1 temperature (T) PW by nitrogen implantation in NMOS poly gates prior to Ni deposition for FUSI; - extending the PMOS PW to lower RTP1 temperatures by improved surface preparation after novel poly etch-back process.
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U2 - 10.1109/VLSIT.2007.4339692
DO - 10.1109/VLSIT.2007.4339692
M3 - Conference article
AN - SCOPUS:47249123629
SP - 200
EP - 201
JO - Digest of Technical Papers - Symposium on VLSI Technology
JF - Digest of Technical Papers - Symposium on VLSI Technology
SN - 0743-1562
M1 - 4339692
T2 - 2007 Symposium on VLSI Technology, VLSIT 2007
Y2 - 12 June 2007 through 14 June 2007
ER -