Strain enhanced FUSI/HfSiON technology with optimized CMOS process window

A. Veloso, P. Verheyen, R. Vos, S. Brus, S. Ito, R. Mitsuhashi, V. Paraschiv, X. Shi, B. Onsia, S. Arnauts, R. Loo, A. Lauwers, T. Conard, J. F. De Marneffe, D. Goossens, D. Baute, S. Locorotondo, T. Chiarella, C. Kerner, C. VranckenS. Mertens, B. J. O'Sullivan, H. Y. Yu, S. Z. Chang, M. Niwa, J. A. Kittl, P. P. Absil, M. Jurczak, T. Hoffmann, S. Biesemans

Research output: Contribution to journalConference articlepeer-review

2 Citations (Scopus)

Abstract

We report, for the first time, a comprehensive study on the compatibility of state-of-the-art performance boosters with FUSI/HfSiON technology, resulting in record high-VT NMOS and PMOS devices with 725/370 μA/μm (at VDD=1.1V, Ioff=20pA/μm and Jg=100/1 mA/cm2). We demonstrate that adding embedded Si0.75Ge0.25 in S/D regions resulted in 45% performance improvement over the FUSI/HfSiON reference, and that the VT distribution is tight and comparable to baseline. For process simplicity purposes, dual phase Ni-FUSI (NiSi NMOS; Ni 31Si12 or Ni2Si PMOS) is formed simultaneously in our integration scheme, each phase having its own process window (PW). In this work, we successfully maximized the common CMOS PW by 2 crucial process improvements: - shining up the NMOS RTP1 temperature (T) PW by nitrogen implantation in NMOS poly gates prior to Ni deposition for FUSI; - extending the PMOS PW to lower RTP1 temperatures by improved surface preparation after novel poly etch-back process.

Original languageEnglish
Article number4339692
Pages (from-to)200-201
Number of pages2
JournalDigest of Technical Papers - Symposium on VLSI Technology
DOIs
Publication statusPublished - 2007
Externally publishedYes
Event2007 Symposium on VLSI Technology, VLSIT 2007 - Kyoto, Japan
Duration: 2007 Jun 122007 Jun 14

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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