We report, for the first time, a comprehensive study on the compatibility of state-of-the-art performance boosters with FUSI/HfSiON technology, resulting in record high-V T NMOS and PMOS devices with 725/370 μA/μm (at V DD =1.1V, Ioff=20pA/μm and Jg=100/1 mA/cm 2 ). We demonstrate that adding embedded Si 0.75 Ge 0.25 in S/D regions resulted in 45% performance improvement over the FUSI/HfSiON reference, and that the V T distribution is tight and comparable to baseline. For process simplicity purposes, dual phase Ni-FUSI (NiSi NMOS; Ni 31 Si 12 or Ni 2 Si PMOS) is formed simultaneously in our integration scheme, each phase having its own process window (PW). In this work, we successfully maximized the common CMOS PW by 2 crucial process improvements: - shining up the NMOS RTP1 temperature (T) PW by nitrogen implantation in NMOS poly gates prior to Ni deposition for FUSI; - extending the PMOS PW to lower RTP1 temperatures by improved surface preparation after novel poly etch-back process.
|Number of pages||2|
|Journal||Digest of Technical Papers - Symposium on VLSI Technology|
|Publication status||Published - 2007 Dec 1|
|Event||2007 Symposium on VLSI Technology, VLSIT 2007 - Kyoto, Japan|
Duration: 2007 Jun 12 → 2007 Jun 14
ASJC Scopus subject areas
- Electrical and Electronic Engineering