STEPPED ELECTRODE TRANSISTOR: SET.

Tetsushi Sakai, Yoshio Sunohara, Yutaka Sakakibara, Junichi Murota

Research output: Contribution to conferencePaperpeer-review

4 Citations (Scopus)

Abstract

SET can achieve high performance without precise photolithography and metallization techniques. An arsenic doped polycrystalline silicon is used as a part of the emitter electrode in the SET structure. It is processed to have an inverse trapezoid shape. Procedure to make the inverse trapezoid shape uses a difference of etching rates between double layers of polycrystalline silicon. Base contact windows are opened through the ion-implantation process followed by chemical etching. The cut off frequency is about 8. 4 GHz. This frequency is higher than that of the conventional planar transistors with equal size emitter by 2 GHz.

Original languageEnglish
Pages43-46
Number of pages4
Publication statusPublished - 1977 Jan 1
EventProc Conf Solid State Devices 8th - Tokyo, Jpn
Duration: 1976 Sep 11976 Sep 3

Other

OtherProc Conf Solid State Devices 8th
CityTokyo, Jpn
Period76/9/176/9/3

ASJC Scopus subject areas

  • Engineering(all)

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