In -The next-generation Internet of Things (IoT) era, it is strongly required to construct new paradigm computer architectures that consume ultra-low power while maintaining high-performance computing. In -The distributed wireless sensor network devices working in a harvested energy environment, power-management techniques play important roles to provide -The best performance with a limited time-dependent energy source. However, in -The present CMOS-only-based VLSI, communication bottlenecks between -The memory and logic modules inside a VLSI chip, as well as increasing standby power dissipation and PVT variation effects, limit -The solutions to -The above problems. In conventional logic-LSI architecture, logic and memory modules are separately implemented, and -These modules are connected to each o-Ther through global interconnections. Even if -The device feature size is scaled down in accordance with -The semiconductor technology roadmap , -The global interconnections are not shortened; ra-Ther, -They are becoming longer, resulting in longer delay and higher power dissipation due to interconnections. In addition, because on-chip memory modules are 'volatile,' -They always consume static power to maintain -The stored data.