SrO capping effect for La2O3/Ce-silicate gate dielectrics

K. Kakushima, K. Okamoto, T. Koyanagi, M. Kouda, K. Tachi, T. Kawanago, J. Song, P. Ahmet, H. Nohira, K. Tsutsui, N. Sugii, T. Hattori, H. Iwai

Research output: Contribution to journalArticlepeer-review

4 Citations (Scopus)

Abstract

The chemical bonding states and electrical characteristics of SrO capped La2O3/CeOx gate dielectric have been examined. Angle-resolved X-ray photoelectron spectroscopy measurement has revealed that Sr atoms diffuse into silicate layer to form SrLa-silicate after annealing. Owing to the incorporation of Sr atoms into silicate layer, a transistor operation with an equivalent oxide thickness (EOT) below 0.5 nm has been demonstrated. A strongly degraded effective electron mobility of 78 cm2/V s at 1 MV/cm has been obtained, which fit well with the general trend in small EOT range below 1 nm. Although process optimization is needed to improve the performance of transistors, Sr capping technique can be useful for EOT scaling.

Original languageEnglish
Pages (from-to)356-359
Number of pages4
JournalMicroelectronics Reliability
Volume50
Issue number3
DOIs
Publication statusPublished - 2010 Mar
Externally publishedYes

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Atomic and Molecular Physics, and Optics
  • Safety, Risk, Reliability and Quality
  • Condensed Matter Physics
  • Surfaces, Coatings and Films
  • Electrical and Electronic Engineering

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