Spread source/drain (SSD) MOSFET using selective silicon growth for 64 Mbit DRAMs

T. Yamada, S. Samata, H. Takato, Y. Matsushita, K. Hieda, A. Nitayama, F. Horiguchi, F. Masuoka

Research output: Contribution to journalConference articlepeer-review

13 Citations (Scopus)


A novel MOSFET structure which has a small occupied area for 64-Mb DRAMs (dynamic RAMs) is proposed. The source-drain regions are raised by using a selective silicon growth technique. Because of lateral growth of the silicon over the gate and the field, the contact area can overlap the gate and the field. Moreover, the shallow source-drain junction of the raised source-drain structure realizes the reduction of the gate length and the isolation spacing. As a result, the MOSFET can minimize the total occupied area. It has been verified that this MOSFET has the potential to realize high-density LSIs such as 64-Mb DRAMs.

Original languageEnglish
Pages (from-to)35-38
Number of pages4
JournalTechnical Digest - International Electron Devices Meeting
Publication statusPublished - 1989 Dec 1
Event1989 International Electron Devices Meeting - Technical Digest - Washington, DC, USA
Duration: 1989 Dec 31989 Dec 6

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry


Dive into the research topics of 'Spread source/drain (SSD) MOSFET using selective silicon growth for 64 Mbit DRAMs'. Together they form a unique fingerprint.

Cite this