Spintronics primitive gate with high error correction efficiency 6(P error) 2 for logic-in memory architecture

Y. Tsuji, R. Nebashi, N. Sakimura, A. Morioka, H. Honjo, K. Tokutome, S. Miura, T. Suzuki, S. Fukami, K. Kinoshita, T. Hanyu, T. Endoh, N. Kasai, H. Ohno, T. Sugibayashi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

12 Citations (Scopus)

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Engineering & Materials Science