Spintronics primitive gate with high error correction efficiency 6(P error) 2 for logic-in memory architecture

Y. Tsuji, R. Nebashi, N. Sakimura, A. Morioka, H. Honjo, K. Tokutome, S. Miura, T. Suzuki, S. Fukami, K. Kinoshita, T. Hanyu, T. Endoh, N. Kasai, H. Ohno, T. Sugibayashi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

12 Citations (Scopus)

Abstract

A spintronics primitive gate with redundancy was designed using domain wall motion (DWM) cells, and the data-missing rate was drastically improved to ∼ 6 (P error) 2 when the error rate per DWM cell was P error. All the DWM cells aligned in series were written simultaneously, which suppressed the increase in power consumption when writing. Application of 4-terminal DWM cells with physically separated current paths for writing and reading saved extra path transistors for redundancy and there were no area overheads.

Original languageEnglish
Title of host publication2012 Symposium on VLSI Technology, VLSIT 2012 - Digest of Technical Papers
Pages63-64
Number of pages2
DOIs
Publication statusPublished - 2012 Sep 27
Event2012 Symposium on VLSI Technology, VLSIT 2012 - Honolulu, HI, United States
Duration: 2012 Jun 122012 Jun 14

Publication series

NameDigest of Technical Papers - Symposium on VLSI Technology
ISSN (Print)0743-1562

Other

Other2012 Symposium on VLSI Technology, VLSIT 2012
CountryUnited States
CityHonolulu, HI
Period12/6/1212/6/14

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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