TY - GEN

T1 - Spike-based time-domain weighted-sum calculation using nanodevices for low power operation

AU - Morie, Takashi

AU - Liang, Haichao

AU - Tohara, Takashi

AU - Tanaka, Hirofumi

AU - Igarashi, Makoto

AU - Samukawa, Seiji

AU - Endo, Kazuhiko

AU - Takahashi, Yasuo

N1 - Funding Information:
This work was supported by JSPS KAKENHI Grant Nos. 22240022 and 15H01706. Part of the work was carried out under the Collaborative Research Project of the Institute of Fluid Science, Tohoku University.

PY - 2016/11/21

Y1 - 2016/11/21

N2 - This paper introduces a time-domain weighted-sum calculation operation based on a spiking neuron model, and discusses a resistance-capacitance circuit that performs a calculation operation assumed to be realized in CMOS VLSI technology. A nanodevice that executes this calculation is also presented. The calculation circuit is useful for extremely low power operation. This operation uses the rising slopes of post-synaptic potentials triggered by input spike pulses. In the time-domain calculation circuit, the energy dissipation is independent of the resistance, and only depends on the capacitance and voltages. However, the time constant, which is the product of the resistance and capacitance, should be relatively large to guarantee the calculation resolution, and therefore the resistance should be at the giga-ohms levels. The nanodevice consists of a nanodisk array connected with a fin field-effect transistor. Nanodisk arrays can be fabricated using a self-assembly bio-nano-template technique, and they act as resistors with resistance levels of several giga-ohms. A weighted sum can be achieved with an energy dissipation on the order of 1 fJ, with a number of inputs that can be more than 100. This amount of energy is several orders of magnitude lower than that of conventional digital processors.

AB - This paper introduces a time-domain weighted-sum calculation operation based on a spiking neuron model, and discusses a resistance-capacitance circuit that performs a calculation operation assumed to be realized in CMOS VLSI technology. A nanodevice that executes this calculation is also presented. The calculation circuit is useful for extremely low power operation. This operation uses the rising slopes of post-synaptic potentials triggered by input spike pulses. In the time-domain calculation circuit, the energy dissipation is independent of the resistance, and only depends on the capacitance and voltages. However, the time constant, which is the product of the resistance and capacitance, should be relatively large to guarantee the calculation resolution, and therefore the resistance should be at the giga-ohms levels. The nanodevice consists of a nanodisk array connected with a fin field-effect transistor. Nanodisk arrays can be fabricated using a self-assembly bio-nano-template technique, and they act as resistors with resistance levels of several giga-ohms. A weighted sum can be achieved with an energy dissipation on the order of 1 fJ, with a number of inputs that can be more than 100. This amount of energy is several orders of magnitude lower than that of conventional digital processors.

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U2 - 10.1109/NANO.2016.7751490

DO - 10.1109/NANO.2016.7751490

M3 - Conference contribution

AN - SCOPUS:85006894305

T3 - 16th International Conference on Nanotechnology - IEEE NANO 2016

SP - 390

EP - 392

BT - 16th International Conference on Nanotechnology - IEEE NANO 2016

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 16th IEEE International Conference on Nanotechnology - IEEE NANO 2016

Y2 - 22 August 2016 through 25 August 2016

ER -