Specification and verification of digital logic and PLCs using an automaton model with delays

Satoru Izumi, Kazuhiro Yamanaka, Yasushi Kato, Kaoru Takahashi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Some techniques and languages which support the design of digital logic hare been traditionally presented. In this paper, we propose a new automaton model which enables to concisely specify digital logic and PLCs Including delay and time-control by Introducing two kinds of delays. Moreover, we develop a support tool which can Intelligibly simulate the behavior of a system specified by this automaton model.

Original languageEnglish
Title of host publication2005 Fifth International Conference on Information, Communications and Signal Processing
Pages1421-1424
Number of pages4
Publication statusPublished - 2005 Dec 1
Externally publishedYes
Event2005 Fifth International Conference on Information, Communications and Signal Processing - Bangkok, Thailand
Duration: 2005 Dec 62005 Dec 9

Publication series

Name2005 Fifth International Conference on Information, Communications and Signal Processing
Volume2005

Other

Other2005 Fifth International Conference on Information, Communications and Signal Processing
CountryThailand
CityBangkok
Period05/12/605/12/9

Keywords

  • Automata
  • Digital logic
  • PLC
  • Specification
  • Verification

ASJC Scopus subject areas

  • Engineering(all)

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