Software pipelining for jetpipeline architecture

Masayuki Katahira, Takehito Sasaki, Hong Shen, Hiroaki Kobayashi, Tadao Nakamura

Research output: Contribution to conferencePaperpeer-review

1 Citation (Scopus)

Abstract

High performance processors based on pipeline processing play an important role in scientific computation. We have proposed a hybrid pipeline architecture named Jetpipeline in our former work. The concept of Jetpipeline comes from the integration of superscalar, VLIW and vector architectures. Jetpipeline has multiple instruction pipelines, which execute multiple instructions like superscalar architectures. Instructions to be executed simultaneously are statically scheduled by a compiler like VLIW architectures. Therefore, parallelism derivation and instruction scheduling are very important for Jetpipeline. Software pipelining is one of the well-known techniques to achieve high throughput when processing loop programs. In this paper, we propose software pipelining for Jetpipeline. Firstly, the overview of the Jetpipeline architecture is described. Then the banked register configuration of Jetpipeline for reducing hardware complexity and supporting software pipelining is presented. Finally, the effectiveness of software pipelining for Jetpipeline is discussed by simulation.

Original languageEnglish
Pages127-134
Number of pages8
Publication statusPublished - 1994 Dec 1
EventProceedings of the International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN) - Kanazawa, Jpn
Duration: 1994 Dec 141994 Dec 16

Other

OtherProceedings of the International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN)
CityKanazawa, Jpn
Period94/12/1494/12/16

ASJC Scopus subject areas

  • Computer Science(all)

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