Single-chip MPEG-2 422P@HL CODEC LSI with multichip configuration for large scale processing beyond HDTV level

Hiroe Iwasaki; Jiro Naganuma; Koyo Nitta; Ken Nakamura; Takeshi Yoshitome; Mitsuo Ogura; Yasuyuki Nakajima; Yutaka Tashiro; Takayuki Onishi; Mitsuo Ikeda; Toshihiro Minami; Makoto Endo; Yoshiyuki Yashima

doi:10.1109/TVLSI.2007.902212

Single-chip MPEG-2 422P@HL CODEC LSI with multichip configuration for large scale processing beyond HDTV level

Hiroe Iwasaki, Jiro Naganuma, Koyo Nitta, Ken Nakamura, Takeshi Yoshitome, Mitsuo Ogura, Yasuyuki Nakajima, Yutaka Tashiro, Takayuki Onishi, Mitsuo Ikeda, Toshihiro Minami, Makoto Endo, Yoshiyuki Yashima

Research output: Contribution to journal › Article › peer-review

5 Citations (Scopus)

Abstract

This paper proposes a new architecture for VASA, a single-chip MPEG-2 422P@HL CODEC LSI with multichip configuration for large scale processing beyond the HDTV level, and demonstrates its flexibility and usefulness. VASA is the world's first single-chip full-specs MPEG-2 422P@HL CODEC LSI with a multichip configuration. An LSI was successfully fabricated using the 0.13-μm eight-metal CMOS process. The architecture not only provides an MPEG-2 422P@HL CODEC but also large scale processing beyond the HDTV level for digital cinema and multiview/-angled live TV applications with a multichip configuration. The VASA implementations will lead to a new dimension in future high-quality, high-resolution digital multimedia entertainment.

Original language	English
Pages (from-to)	1055-1059
Number of pages	5
Journal	IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume	15
Issue number	9
DOIs	https://doi.org/10.1109/TVLSI.2007.902212
Publication status	Published - 2007 Sep
Externally published	Yes

Keywords

Embedded system
High performance
MPEG-2 CODEC
System-on-chips

ASJC Scopus subject areas

Software
Hardware and Architecture
Electrical and Electronic Engineering

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10.1109/TVLSI.2007.902212

Cite this

Iwasaki, H., Naganuma, J., Nitta, K., Nakamura, K., Yoshitome, T., Ogura, M., Nakajima, Y., Tashiro, Y., Onishi, T., Ikeda, M., Minami, T., Endo, M., & Yashima, Y. (2007). Single-chip MPEG-2 422P@HL CODEC LSI with multichip configuration for large scale processing beyond HDTV level. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 15(9), 1055-1059. https://doi.org/10.1109/TVLSI.2007.902212

Single-chip MPEG-2 422P@HL CODEC LSI with multichip configuration for large scale processing beyond HDTV level. / Iwasaki, Hiroe; Naganuma, Jiro; Nitta, Koyo; Nakamura, Ken; Yoshitome, Takeshi; Ogura, Mitsuo; Nakajima, Yasuyuki; Tashiro, Yutaka; Onishi, Takayuki; Ikeda, Mitsuo; Minami, Toshihiro; Endo, Makoto; Yashima, Yoshiyuki.

In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 15, No. 9, 09.2007, p. 1055-1059.

Research output: Contribution to journal › Article › peer-review

Iwasaki, H, Naganuma, J, Nitta, K, Nakamura, K, Yoshitome, T, Ogura, M, Nakajima, Y, Tashiro, Y, Onishi, T, Ikeda, M, Minami, T, Endo, M & Yashima, Y 2007, 'Single-chip MPEG-2 422P@HL CODEC LSI with multichip configuration for large scale processing beyond HDTV level', IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 15, no. 9, pp. 1055-1059. https://doi.org/10.1109/TVLSI.2007.902212

Iwasaki, Hiroe ; Naganuma, Jiro ; Nitta, Koyo ; Nakamura, Ken ; Yoshitome, Takeshi ; Ogura, Mitsuo ; Nakajima, Yasuyuki ; Tashiro, Yutaka ; Onishi, Takayuki ; Ikeda, Mitsuo ; Minami, Toshihiro ; Endo, Makoto ; Yashima, Yoshiyuki. / Single-chip MPEG-2 422P@HL CODEC LSI with multichip configuration for large scale processing beyond HDTV level. In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2007 ; Vol. 15, No. 9. pp. 1055-1059.

@article{8036a45c8ed84d6e9f8c998433935e80,

title = "Single-chip MPEG-2 422P@HL CODEC LSI with multichip configuration for large scale processing beyond HDTV level",

abstract = "This paper proposes a new architecture for VASA, a single-chip MPEG-2 422P@HL CODEC LSI with multichip configuration for large scale processing beyond the HDTV level, and demonstrates its flexibility and usefulness. VASA is the world's first single-chip full-specs MPEG-2 422P@HL CODEC LSI with a multichip configuration. An LSI was successfully fabricated using the 0.13-μm eight-metal CMOS process. The architecture not only provides an MPEG-2 422P@HL CODEC but also large scale processing beyond the HDTV level for digital cinema and multiview/-angled live TV applications with a multichip configuration. The VASA implementations will lead to a new dimension in future high-quality, high-resolution digital multimedia entertainment.",

keywords = "Embedded system, High performance, MPEG-2 CODEC, System-on-chips",

author = "Hiroe Iwasaki and Jiro Naganuma and Koyo Nitta and Ken Nakamura and Takeshi Yoshitome and Mitsuo Ogura and Yasuyuki Nakajima and Yutaka Tashiro and Takayuki Onishi and Mitsuo Ikeda and Toshihiro Minami and Makoto Endo and Yoshiyuki Yashima",

year = "2007",

month = sep,

doi = "10.1109/TVLSI.2007.902212",

language = "English",

volume = "15",

pages = "1055--1059",

journal = "IEEE Transactions on Very Large Scale Integration (VLSI) Systems",

issn = "1063-8210",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "9",

}

TY - JOUR

T1 - Single-chip MPEG-2 422P@HL CODEC LSI with multichip configuration for large scale processing beyond HDTV level

AU - Iwasaki, Hiroe

AU - Naganuma, Jiro

AU - Nitta, Koyo

AU - Nakamura, Ken

AU - Yoshitome, Takeshi

AU - Ogura, Mitsuo

AU - Nakajima, Yasuyuki

AU - Tashiro, Yutaka

AU - Onishi, Takayuki

AU - Ikeda, Mitsuo

AU - Minami, Toshihiro

AU - Endo, Makoto

AU - Yashima, Yoshiyuki

PY - 2007/9

Y1 - 2007/9

N2 - This paper proposes a new architecture for VASA, a single-chip MPEG-2 422P@HL CODEC LSI with multichip configuration for large scale processing beyond the HDTV level, and demonstrates its flexibility and usefulness. VASA is the world's first single-chip full-specs MPEG-2 422P@HL CODEC LSI with a multichip configuration. An LSI was successfully fabricated using the 0.13-μm eight-metal CMOS process. The architecture not only provides an MPEG-2 422P@HL CODEC but also large scale processing beyond the HDTV level for digital cinema and multiview/-angled live TV applications with a multichip configuration. The VASA implementations will lead to a new dimension in future high-quality, high-resolution digital multimedia entertainment.

AB - This paper proposes a new architecture for VASA, a single-chip MPEG-2 422P@HL CODEC LSI with multichip configuration for large scale processing beyond the HDTV level, and demonstrates its flexibility and usefulness. VASA is the world's first single-chip full-specs MPEG-2 422P@HL CODEC LSI with a multichip configuration. An LSI was successfully fabricated using the 0.13-μm eight-metal CMOS process. The architecture not only provides an MPEG-2 422P@HL CODEC but also large scale processing beyond the HDTV level for digital cinema and multiview/-angled live TV applications with a multichip configuration. The VASA implementations will lead to a new dimension in future high-quality, high-resolution digital multimedia entertainment.

KW - Embedded system

KW - High performance

KW - MPEG-2 CODEC

KW - System-on-chips

UR - http://www.scopus.com/inward/record.url?scp=34548079847&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=34548079847&partnerID=8YFLogxK

U2 - 10.1109/TVLSI.2007.902212

DO - 10.1109/TVLSI.2007.902212

M3 - Article

AN - SCOPUS:34548079847

VL - 15

SP - 1055

EP - 1059

JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

SN - 1063-8210

IS - 9

ER -

Single-chip MPEG-2 422P@HL CODEC LSI with multichip configuration for large scale processing beyond HDTV level

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Keywords

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