Single-chip 5.8 GHz ETC transceiver IC with PLL and demodulation circuits using SiGe HBT/CMOS

Toru Masuda, Ken Ichi Ohhata, Nobuhiro Shiramizu, Satoshi Hanazawa, Masaki Kudoh, Yuko Tanba, Yusuke Takeuchi, Hiromi Shimamoto, Toshio Nagashima, Katsuyoshi Washio

Research output: Contribution to journalConference articlepeer-review

23 Citations (Scopus)

Abstract

A single-chip 5.8 GHz ETC transceiver IC with PLL and demodulator uses SiGe HBT/CMOS. The fully integrated ETC chip includes a 31 dB- gain RX stage, an ASK demodulator, and a high-precision RSSI. The PLL is constructed with a varactor-tuned LC-VCO and a low-power BiCMOS synthesizer. The TX stage incorporates a transformer-transferred single-ended PA.

Original languageEnglish
Pages (from-to)96-97+449+85
JournalDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Publication statusPublished - 2002 Jan 1
Externally publishedYes
Event2002 IEEE International Solid-State Circuits Conference - San Francisco, CA, United States
Duration: 2002 Feb 32002 Feb 7

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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