Si substrate resistivity design for on-chip matching circuit based on electro-magnetic simulation

Masayoshi Ono, Noriharu Suematsu, Shunji Kubo, Kensuke Nakajima, Yoshitada Iyama, Tadashi Takagi, Osami Ishida

Research output: Contribution to journalArticle

10 Citations (Scopus)

Abstract

For on-chip matching Si-MMIC fabricated on a conventional low resistivity Si substrate, the loss of on-chip inductors is quite high due to the dielectric loss of the substrate. In order to reduce the loss of on-chip matching circuit, the use of high resistivity Si substrate is quite effective. By using electromagnetic simulation, the relationship between coplanar waveguide (CPW) transmission line characteristics and the resistivity of Si substrate is discussed. Based on the simulated results, the resistivity of Si substrate is designed to achieve lower dielectric loss than conductor loss. The effectiveness of high resistivity Si substrate is evaluated by the extraction of equivalent circuit model parameters of the fabricated on-chip spiral inductors and the measurement of the fabricated on-chip matching Si-MMIC LNA's.

Original languageEnglish
Pages (from-to)923-930
Number of pages8
JournalIEICE Transactions on Electronics
VolumeE84-C
Issue number7
Publication statusPublished - 2001 Jul
Externally publishedYes

Keywords

  • Electro-magnetic simulation
  • High resistivity Si substrate
  • Low noise amplifier
  • Si-MMIC
  • Spiral inductor

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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  • Cite this

    Ono, M., Suematsu, N., Kubo, S., Nakajima, K., Iyama, Y., Takagi, T., & Ishida, O. (2001). Si substrate resistivity design for on-chip matching circuit based on electro-magnetic simulation. IEICE Transactions on Electronics, E84-C(7), 923-930.