Set-valued logic circuits for next generation VLSI architectures

Takafumi Aoki; Tatsuo Higuchi

Set-valued logic circuits for next generation VLSI architectures

Takafumi Aoki, Tatsuo Higuchi

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Research output: Contribution to journal › Conference article › peer-review

2 Citations (Scopus)

Abstract

This paper presents the concept of `set-valued logic' as a foundation for next-generation integrated systems free from interconnection problems. The set-valued logic system employs multiplexable information carriers to achieve highly parallel processing with reduced interconnections. This paper also proposes a new approach to the construction of set-valued logic VLSIs employing pseudo-random sequences as information carriers.

Original language	English
Pages (from-to)	140-147
Number of pages	8
Journal	Proceedings of The International Symposium on Multiple-Valued Logic
Publication status	Published - 1998 Jan 1
Event	Proceedings of the 1998 28th International Symposium on Multiple-Valued Logic - Fukuoka, Jpn Duration: 1998 May 27 → 1998 May 29

ASJC Scopus subject areas

Chemical Health and Safety
Hardware and Architecture
Safety, Risk, Reliability and Quality
Logic

Cite this

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title = "Set-valued logic circuits for next generation VLSI architectures",

abstract = "This paper presents the concept of `set-valued logic' as a foundation for next-generation integrated systems free from interconnection problems. The set-valued logic system employs multiplexable information carriers to achieve highly parallel processing with reduced interconnections. This paper also proposes a new approach to the construction of set-valued logic VLSIs employing pseudo-random sequences as information carriers.",

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AU - Higuchi, Tatsuo

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AB - This paper presents the concept of `set-valued logic' as a foundation for next-generation integrated systems free from interconnection problems. The set-valued logic system employs multiplexable information carriers to achieve highly parallel processing with reduced interconnections. This paper also proposes a new approach to the construction of set-valued logic VLSIs employing pseudo-random sequences as information carriers.

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M3 - Conference article

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JO - Proceedings of The International Symposium on Multiple-Valued Logic

JF - Proceedings of The International Symposium on Multiple-Valued Logic

SN - 0195-623X

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Y2 - 27 May 1998 through 29 May 1998

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Set-valued logic circuits for next generation VLSI architectures

Abstract

ASJC Scopus subject areas

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