Self-assembly technology for reconfigured wafer-to-wafer 3D integration

T. Fukushima, E. Iwata, K. W. Lee, T. Tanaka, M. Koyanagi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

21 Citations (Scopus)

Abstract

We have introduced a new 3D stacking technology called reconfigured wafer-to-wafer 3D integration using surface tension-powered multichip self-assembly and multichip transfer techniques. Many Si chips were simultaneously selfassembled to a carrier wafer named "reconfigured wafer". High-precision chip alignment with sub-micron-scale accuracy can be realized by optimizing self-assembly conditions. In addition, we developed a new self-assembled multichip bonder to three-dimensionally stack many known good dies (KDGs) on 8-inch wafers at the wafer level. By using the equipment, the many self-assembled Si chips were transferred to another target wafer in batch.

Original languageEnglish
Title of host publication2010 Proceedings 60th Electronic Components and Technology Conference, ECTC 2010
Pages1050-1055
Number of pages6
DOIs
Publication statusPublished - 2010 Aug 9
Event60th Electronic Components and Technology Conference, ECTC 2010 - Las Vegas, NV, United States
Duration: 2010 Jun 12010 Jun 4

Publication series

NameProceedings - Electronic Components and Technology Conference
ISSN (Print)0569-5503

Other

Other60th Electronic Components and Technology Conference, ECTC 2010
CountryUnited States
CityLas Vegas, NV
Period10/6/110/6/4

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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