Self-assembly technology for reconfigured wafer-to-wafer 3D integration

T. Fukushima; E. Iwata; K. W. Lee; T. Tanaka; M. Koyanagi

doi:10.1109/ECTC.2010.5490830

Self-assembly technology for reconfigured wafer-to-wafer 3D integration

T. Fukushima, E. Iwata, K. W. Lee, T. Tanaka, M. Koyanagi

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

21 Citations (Scopus)

Abstract

We have introduced a new 3D stacking technology called reconfigured wafer-to-wafer 3D integration using surface tension-powered multichip self-assembly and multichip transfer techniques. Many Si chips were simultaneously selfassembled to a carrier wafer named "reconfigured wafer". High-precision chip alignment with sub-micron-scale accuracy can be realized by optimizing self-assembly conditions. In addition, we developed a new self-assembled multichip bonder to three-dimensionally stack many known good dies (KDGs) on 8-inch wafers at the wafer level. By using the equipment, the many self-assembled Si chips were transferred to another target wafer in batch.

Original language	English
Title of host publication	2010 Proceedings 60th Electronic Components and Technology Conference, ECTC 2010
Pages	1050-1055
Number of pages	6
DOIs	https://doi.org/10.1109/ECTC.2010.5490830
Publication status	Published - 2010 Aug 9
Event	60th Electronic Components and Technology Conference, ECTC 2010 - Las Vegas, NV, United States Duration: 2010 Jun 1 → 2010 Jun 4

Publication series

Name	Proceedings - Electronic Components and Technology Conference
ISSN (Print)	0569-5503

Other

Other	60th Electronic Components and Technology Conference, ECTC 2010
Country	United States
City	Las Vegas, NV
Period	10/6/1 → 10/6/4

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

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Self-assembly technology for reconfigured wafer-to-wafer 3D integration. / Fukushima, T.; Iwata, E.; Lee, K. W.; Tanaka, T.; Koyanagi, M.

2010 Proceedings 60th Electronic Components and Technology Conference, ECTC 2010. 2010. p. 1050-1055 5490830 (Proceedings - Electronic Components and Technology Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Fukushima, T, Iwata, E, Lee, KW, Tanaka, T & Koyanagi, M 2010, Self-assembly technology for reconfigured wafer-to-wafer 3D integration. in 2010 Proceedings 60th Electronic Components and Technology Conference, ECTC 2010., 5490830, Proceedings - Electronic Components and Technology Conference, pp. 1050-1055, 60th Electronic Components and Technology Conference, ECTC 2010, Las Vegas, NV, United States, 10/6/1. https://doi.org/10.1109/ECTC.2010.5490830

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abstract = "We have introduced a new 3D stacking technology called reconfigured wafer-to-wafer 3D integration using surface tension-powered multichip self-assembly and multichip transfer techniques. Many Si chips were simultaneously selfassembled to a carrier wafer named {"}reconfigured wafer{"}. High-precision chip alignment with sub-micron-scale accuracy can be realized by optimizing self-assembly conditions. In addition, we developed a new self-assembled multichip bonder to three-dimensionally stack many known good dies (KDGs) on 8-inch wafers at the wafer level. By using the equipment, the many self-assembled Si chips were transferred to another target wafer in batch.",

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AB - We have introduced a new 3D stacking technology called reconfigured wafer-to-wafer 3D integration using surface tension-powered multichip self-assembly and multichip transfer techniques. Many Si chips were simultaneously selfassembled to a carrier wafer named "reconfigured wafer". High-precision chip alignment with sub-micron-scale accuracy can be realized by optimizing self-assembly conditions. In addition, we developed a new self-assembled multichip bonder to three-dimensionally stack many known good dies (KDGs) on 8-inch wafers at the wafer level. By using the equipment, the many self-assembled Si chips were transferred to another target wafer in batch.

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Self-assembly technology for reconfigured wafer-to-wafer 3D integration

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