Self-assembly process for chip-to-wafer three-dimensional integration

T. Fukushima; Y. Yamada; H. Kikuchi; T. Tanaka; M. Koyanagi

doi:10.1109/ECTC.2007.373895

Self-assembly process for chip-to-wafer three-dimensional integration

T. Fukushima, Y. Yamada, H. Kikuchi, T. Tanaka, M. Koyanagi

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

27 Citations (Scopus)

Abstract

We have proposed chip-to-wafer stacking for three-dimensional (3D) integration. To realize the chip-to-wafer 3D integration, five key technologies of through-Si interconnection and microbump formation, chip-to-wafer alignment, underfilling, and chip thinning were investigated. Three-layer stacked chips with a layer thickness of several tens microns were fabricated by using the key technologies. Each chip was serially and mechanically aligned and bonded onto a support LSI wafer. In addition, we newly introduce a stacking technique using self-assembly as a key process for advanced chip-to-wafer 3D integration. High-precision alignment with an accuracy of within 1 μm was obtained and stacking throughput can be dramatically improved by the self-assembly.

Original language	English
Title of host publication	Proceedings - 57th Electronic Components and Technology Conference 2007, ECTC '07
Pages	836-841
Number of pages	6
DOIs	https://doi.org/10.1109/ECTC.2007.373895
Publication status	Published - 2007 Oct 22
Event	57th Electronic Components and Technology Conference 2007, ECTC '07 - Sparks, NV, United States Duration: 2007 May 29 → 2007 Jun 1

Publication series

Name	Proceedings - Electronic Components and Technology Conference
ISSN (Print)	0569-5503

Other

Other	57th Electronic Components and Technology Conference 2007, ECTC '07
Country	United States
City	Sparks, NV
Period	07/5/29 → 07/6/1

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Access to Document

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Fukushima, T., Yamada, Y., Kikuchi, H., Tanaka, T., & Koyanagi, M. (2007). Self-assembly process for chip-to-wafer three-dimensional integration. In Proceedings - 57th Electronic Components and Technology Conference 2007, ECTC '07 (pp. 836-841). [4249981] (Proceedings - Electronic Components and Technology Conference). https://doi.org/10.1109/ECTC.2007.373895

Self-assembly process for chip-to-wafer three-dimensional integration. / Fukushima, T.; Yamada, Y.; Kikuchi, H.; Tanaka, T.; Koyanagi, M.

Proceedings - 57th Electronic Components and Technology Conference 2007, ECTC '07. 2007. p. 836-841 4249981 (Proceedings - Electronic Components and Technology Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Fukushima, T, Yamada, Y, Kikuchi, H, Tanaka, T & Koyanagi, M 2007, Self-assembly process for chip-to-wafer three-dimensional integration. in Proceedings - 57th Electronic Components and Technology Conference 2007, ECTC '07., 4249981, Proceedings - Electronic Components and Technology Conference, pp. 836-841, 57th Electronic Components and Technology Conference 2007, ECTC '07, Sparks, NV, United States, 07/5/29. https://doi.org/10.1109/ECTC.2007.373895

@inproceedings{eac84ef69bb24e638ceefaa8cfbaf7f2,

title = "Self-assembly process for chip-to-wafer three-dimensional integration",

abstract = "We have proposed chip-to-wafer stacking for three-dimensional (3D) integration. To realize the chip-to-wafer 3D integration, five key technologies of through-Si interconnection and microbump formation, chip-to-wafer alignment, underfilling, and chip thinning were investigated. Three-layer stacked chips with a layer thickness of several tens microns were fabricated by using the key technologies. Each chip was serially and mechanically aligned and bonded onto a support LSI wafer. In addition, we newly introduce a stacking technique using self-assembly as a key process for advanced chip-to-wafer 3D integration. High-precision alignment with an accuracy of within 1 μm was obtained and stacking throughput can be dramatically improved by the self-assembly.",

author = "T. Fukushima and Y. Yamada and H. Kikuchi and T. Tanaka and M. Koyanagi",

year = "2007",

month = oct,

day = "22",

doi = "10.1109/ECTC.2007.373895",

language = "English",

isbn = "1424409853",

series = "Proceedings - Electronic Components and Technology Conference",

pages = "836--841",

booktitle = "Proceedings - 57th Electronic Components and Technology Conference 2007, ECTC '07",

note = "57th Electronic Components and Technology Conference 2007, ECTC '07 ; Conference date: 29-05-2007 Through 01-06-2007",

}

TY - GEN

T1 - Self-assembly process for chip-to-wafer three-dimensional integration

AU - Fukushima, T.

AU - Yamada, Y.

AU - Kikuchi, H.

AU - Tanaka, T.

AU - Koyanagi, M.

PY - 2007/10/22

Y1 - 2007/10/22

N2 - We have proposed chip-to-wafer stacking for three-dimensional (3D) integration. To realize the chip-to-wafer 3D integration, five key technologies of through-Si interconnection and microbump formation, chip-to-wafer alignment, underfilling, and chip thinning were investigated. Three-layer stacked chips with a layer thickness of several tens microns were fabricated by using the key technologies. Each chip was serially and mechanically aligned and bonded onto a support LSI wafer. In addition, we newly introduce a stacking technique using self-assembly as a key process for advanced chip-to-wafer 3D integration. High-precision alignment with an accuracy of within 1 μm was obtained and stacking throughput can be dramatically improved by the self-assembly.

AB - We have proposed chip-to-wafer stacking for three-dimensional (3D) integration. To realize the chip-to-wafer 3D integration, five key technologies of through-Si interconnection and microbump formation, chip-to-wafer alignment, underfilling, and chip thinning were investigated. Three-layer stacked chips with a layer thickness of several tens microns were fabricated by using the key technologies. Each chip was serially and mechanically aligned and bonded onto a support LSI wafer. In addition, we newly introduce a stacking technique using self-assembly as a key process for advanced chip-to-wafer 3D integration. High-precision alignment with an accuracy of within 1 μm was obtained and stacking throughput can be dramatically improved by the self-assembly.

UR - http://www.scopus.com/inward/record.url?scp=35348855658&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=35348855658&partnerID=8YFLogxK

U2 - 10.1109/ECTC.2007.373895

DO - 10.1109/ECTC.2007.373895

M3 - Conference contribution

AN - SCOPUS:35348855658

SN - 1424409853

SN - 9781424409853

T3 - Proceedings - Electronic Components and Technology Conference

SP - 836

EP - 841

BT - Proceedings - 57th Electronic Components and Technology Conference 2007, ECTC '07

T2 - 57th Electronic Components and Technology Conference 2007, ECTC '07

Y2 - 29 May 2007 through 1 June 2007

ER -