Self-assembly process for chip-to-wafer three-dimensional integration

T. Fukushima, Y. Yamada, H. Kikuchi, T. Tanaka, M. Koyanagi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

30 Citations (Scopus)


We have proposed chip-to-wafer stacking for three-dimensional (3D) integration. To realize the chip-to-wafer 3D integration, five key technologies of through-Si interconnection and microbump formation, chip-to-wafer alignment, underfilling, and chip thinning were investigated. Three-layer stacked chips with a layer thickness of several tens microns were fabricated by using the key technologies. Each chip was serially and mechanically aligned and bonded onto a support LSI wafer. In addition, we newly introduce a stacking technique using self-assembly as a key process for advanced chip-to-wafer 3D integration. High-precision alignment with an accuracy of within 1 μm was obtained and stacking throughput can be dramatically improved by the self-assembly.

Original languageEnglish
Title of host publicationProceedings - 57th Electronic Components and Technology Conference 2007, ECTC '07
Number of pages6
Publication statusPublished - 2007
Event57th Electronic Components and Technology Conference 2007, ECTC '07 - Sparks, NV, United States
Duration: 2007 May 292007 Jun 1

Publication series

NameProceedings - Electronic Components and Technology Conference
ISSN (Print)0569-5503


Other57th Electronic Components and Technology Conference 2007, ECTC '07
Country/TerritoryUnited States
CitySparks, NV

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering


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