Self-Assembly and Electrostatic Carrier Technology for Via-Last TSV Formation Using Transfer Stacking-Based Chip-to-Wafer 3-D Integration

Hideto Hashiguchi, Takafumi Fukushima, Hiroyuki Hashimoto, Ji Cheol Bea, Mariappan Murugesan, Hisashi Kino, Tetsu Tanaka, Mitsumasa Koyanagi

Research output: Contribution to journalArticlepeer-review

8 Citations (Scopus)

Abstract

A self-assembly and electrostatic (SAE) carrier technology is developed for high-precision and high-throughput chip-to-wafer 3-D integration. In this paper, water surface tension-driven chip assembly is combined with electrostatic adhesion to keep high alignment accuracies obtained by the capillary self-assembly process. The self-assembled chips can be firmly fixed on an SAE carrier wafer by electrostatic adhesion, and then, the chips can be readily detached from the carrier by discharging and transferred to another carrier with a temporary adhesive. This paper describes the impact of chip clamping forces and electrical reliability of the SAE carrier on chips to be 3-D stacked in chip-to-wafer configuration. Through-Si via formation is demonstrated by using a via-last 3-D integration process based on the SAE carrier. The demonstration shows that the SAE carrier maintains higher chip alignment accuracies than does conventional carrier without electrostatic adhesion.

Original languageEnglish
Article number8101564
Pages (from-to)5065-5072
Number of pages8
JournalIEEE Transactions on Electron Devices
Volume64
Issue number12
DOIs
Publication statusPublished - 2017 Dec

Keywords

  • Capillary self-assembly
  • chip-to-wafer 3-D integration
  • electrostatic adhesion
  • temporary bonding/debonding
  • transfer stacking

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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