Self-aligned ultra thin HFO 2 CMOS transistors with high quality CVD TaN gate electrode

C. H. Lee, J. J. Lee, W. P. Bai, S. H. Bae, J. H. Sim, X. Lei, R. D. Clark, Y. Harada, Masaaki Niwa, D. L. Kwong

Research output: Contribution to conferencePaper

19 Citations (Scopus)

Abstract

In this paper, we have demonstrated and characterized self-aligned, gate-first CVD TaN gate n- and p-MOS transistors with ultra thin (EOT=11∼12Å) CVD HFO 2 gate dielectrics. These transistors show no sign of gate deletion and excellent thermal stability after 1000°C, 30s N 2 anneal. Compared with PVD TaN devices, the CVD TaN/HfO 2 devices exhibit lower leakage current, smaller CV hysteresis, superior interface properties, higher transconductance, and superior electron and hole mobility.

Original languageEnglish
Pages82-83
Number of pages2
Publication statusPublished - 2002 Jan 1
Externally publishedYes
Event2002 Symposium on VLSI Technology Digest of Technical Papers - Honolulu, HI, United States
Duration: 2002 Jun 112002 Jun 13

Other

Other2002 Symposium on VLSI Technology Digest of Technical Papers
CountryUnited States
CityHonolulu, HI
Period02/6/1102/6/13

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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    Lee, C. H., Lee, J. J., Bai, W. P., Bae, S. H., Sim, J. H., Lei, X., Clark, R. D., Harada, Y., Niwa, M., & Kwong, D. L. (2002). Self-aligned ultra thin HFO 2 CMOS transistors with high quality CVD TaN gate electrode . 82-83. Paper presented at 2002 Symposium on VLSI Technology Digest of Technical Papers, Honolulu, HI, United States.