Self-Aligned Complementary Bipolar Technology for Low-Power Dissipation and Ultra-High-Speed LSI's

Takahiro Onai, Eiji Ohue, Yohji Idei, Katsuyoshi Washio, Tohru Nakamura, Masamichi Tanabe, Hiromi Shimamoto

Research output: Contribution to journalArticlepeer-review

9 Citations (Scopus)

Abstract

Fully symmetrical complementary bipolar transistors for low power-dissipation and ultra-high-speed LSI's have been integrated in the same chip using a 0.3-µm SPOTEC process. Reducing the surface concentration of the boron by oxidation at the surface of the boron diffusion layer suppressed the upward diffusion of boron from the subcollector of the pnp transistor during epitaxial growth. This enabled thin epitaxial layer growth for both npn and pnp transistors simultaneously. Cutoff frequencies of 30 and 32 GHz were obtained in npn and pnp transistors, respectively. Simulated results showed that the power dissipation is reduced to 1/5 in a complementary active pull-down circuit compared with an ECL circuit.

Original languageEnglish
Pages (from-to)413-418
Number of pages6
JournalIEEE Transactions on Electron Devices
Volume42
Issue number3
DOIs
Publication statusPublished - 1995 Jan 1
Externally publishedYes

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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