Self-Aligned Complementary Bipolar Technology for Low-Power Dissipation and Ultra-High-Speed LSI's

Takahiro Onai; Eiji Ohue; Yohji Idei; Katsuyoshi Washio; Tohru Nakamura; Masamichi Tanabe; Hiromi Shimamoto

doi:10.1109/16.368037

Self-Aligned Complementary Bipolar Technology for Low-Power Dissipation and Ultra-High-Speed LSI's

Takahiro Onai, Eiji Ohue, Yohji Idei, Katsuyoshi Washio, Tohru Nakamura, Masamichi Tanabe, Hiromi Shimamoto

Research output: Contribution to journal › Article › peer-review

9 Citations (Scopus)

Abstract

Fully symmetrical complementary bipolar transistors for low power-dissipation and ultra-high-speed LSI's have been integrated in the same chip using a 0.3-µm SPOTEC process. Reducing the surface concentration of the boron by oxidation at the surface of the boron diffusion layer suppressed the upward diffusion of boron from the subcollector of the pnp transistor during epitaxial growth. This enabled thin epitaxial layer growth for both npn and pnp transistors simultaneously. Cutoff frequencies of 30 and 32 GHz were obtained in npn and pnp transistors, respectively. Simulated results showed that the power dissipation is reduced to 1/5 in a complementary active pull-down circuit compared with an ECL circuit.

Original language	English
Pages (from-to)	413-418
Number of pages	6
Journal	IEEE Transactions on Electron Devices
Volume	42
Issue number	3
DOIs	https://doi.org/10.1109/16.368037
Publication status	Published - 1995 Mar
Externally published	Yes

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Access to Document

10.1109/16.368037

Cite this

@article{312660051062488a82b9b3d2fa64350f,

title = "Self-Aligned Complementary Bipolar Technology for Low-Power Dissipation and Ultra-High-Speed LSI's",

abstract = "Fully symmetrical complementary bipolar transistors for low power-dissipation and ultra-high-speed LSI's have been integrated in the same chip using a 0.3-µm SPOTEC process. Reducing the surface concentration of the boron by oxidation at the surface of the boron diffusion layer suppressed the upward diffusion of boron from the subcollector of the pnp transistor during epitaxial growth. This enabled thin epitaxial layer growth for both npn and pnp transistors simultaneously. Cutoff frequencies of 30 and 32 GHz were obtained in npn and pnp transistors, respectively. Simulated results showed that the power dissipation is reduced to 1/5 in a complementary active pull-down circuit compared with an ECL circuit.",

author = "Takahiro Onai and Eiji Ohue and Yohji Idei and Katsuyoshi Washio and Tohru Nakamura and Masamichi Tanabe and Hiromi Shimamoto",

year = "1995",

month = mar,

doi = "10.1109/16.368037",

language = "English",

volume = "42",

pages = "413--418",

journal = "IEEE Transactions on Electron Devices",

issn = "0018-9383",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "3",

}

TY - JOUR

T1 - Self-Aligned Complementary Bipolar Technology for Low-Power Dissipation and Ultra-High-Speed LSI's

AU - Onai, Takahiro

AU - Ohue, Eiji

AU - Idei, Yohji

AU - Washio, Katsuyoshi

AU - Nakamura, Tohru

AU - Tanabe, Masamichi

AU - Shimamoto, Hiromi

PY - 1995/3

Y1 - 1995/3

N2 - Fully symmetrical complementary bipolar transistors for low power-dissipation and ultra-high-speed LSI's have been integrated in the same chip using a 0.3-µm SPOTEC process. Reducing the surface concentration of the boron by oxidation at the surface of the boron diffusion layer suppressed the upward diffusion of boron from the subcollector of the pnp transistor during epitaxial growth. This enabled thin epitaxial layer growth for both npn and pnp transistors simultaneously. Cutoff frequencies of 30 and 32 GHz were obtained in npn and pnp transistors, respectively. Simulated results showed that the power dissipation is reduced to 1/5 in a complementary active pull-down circuit compared with an ECL circuit.

AB - Fully symmetrical complementary bipolar transistors for low power-dissipation and ultra-high-speed LSI's have been integrated in the same chip using a 0.3-µm SPOTEC process. Reducing the surface concentration of the boron by oxidation at the surface of the boron diffusion layer suppressed the upward diffusion of boron from the subcollector of the pnp transistor during epitaxial growth. This enabled thin epitaxial layer growth for both npn and pnp transistors simultaneously. Cutoff frequencies of 30 and 32 GHz were obtained in npn and pnp transistors, respectively. Simulated results showed that the power dissipation is reduced to 1/5 in a complementary active pull-down circuit compared with an ECL circuit.

UR - http://www.scopus.com/inward/record.url?scp=0029271411&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0029271411&partnerID=8YFLogxK

U2 - 10.1109/16.368037

DO - 10.1109/16.368037

M3 - Article

AN - SCOPUS:0029271411

VL - 42

SP - 413

EP - 418

JO - IEEE Transactions on Electron Devices

JF - IEEE Transactions on Electron Devices

SN - 0018-9383

IS - 3

ER -

Self-Aligned Complementary Bipolar Technology for Low-Power Dissipation and Ultra-High-Speed LSI's

Abstract

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this