Abstract
A novel self-aligned insulation for silicon gates is realized by a new technique of selective oxide coating of silicon gates (SELOCS). This SELOCS utilizes concentration-dependent oxidation and diffusion-defined uniform etching. As the entire surface of a phosphorus-doped polysilicon gate is uniformly covered with its own oxide, SELOCS technology provides a nearly zero registration tolerance between the photoengraving of S&D contact holes and the gate. Consequently, almost one half of area reduction ratio is obtained without requiring finer pattern lithography.
Original language | English |
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Pages | 255-260 |
Number of pages | 6 |
Publication status | Published - 1979 Jan 1 |
Event | Proc Conf Solid State Devices 10th - Tokyo, Jpn Duration: 1978 Aug 29 → 1978 Aug 30 |
Other
Other | Proc Conf Solid State Devices 10th |
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City | Tokyo, Jpn |
Period | 78/8/29 → 78/8/30 |
ASJC Scopus subject areas
- Engineering(all)