Selective decoding in associative memories based on Sparse-Clustered Networks

Hooman Jarollahi, Naoya Onizawa, Warren J. Gross

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Abstract

Associative memories are structures that can retrieve previously stored information given a partial input pattern instead of an explicit address as in indexed memories. A few hardware approaches have recently been introduced for a new family of associative memories based on Sparse-Clustered Networks (SCN) that show attractive features. These architectures are suitable for implementations with low retrieval latency, but are limited to small networks that store a few hundred data entries. In this paper, a new hardware architecture of SCNs is proposed that features a new data-storage technique as well as a method we refer to as Selective Decoding (SD-SCN). The SD-SCN has been implemented using a similar FPGA used in the previous efforts and achieves two orders of magnitude higher capacity, with no error-performance penalty but with the cost of few extra clock cycles per data access.

Original languageEnglish
Title of host publication2013 IEEE Global Conference on Signal and Information Processing, GlobalSIP 2013 - Proceedings
Pages1270-1273
Number of pages4
DOIs
Publication statusPublished - 2013 Dec 1
Externally publishedYes
Event2013 1st IEEE Global Conference on Signal and Information Processing, GlobalSIP 2013 - Austin, TX, United States
Duration: 2013 Dec 32013 Dec 5

Publication series

Name2013 IEEE Global Conference on Signal and Information Processing, GlobalSIP 2013 - Proceedings

Conference

Conference2013 1st IEEE Global Conference on Signal and Information Processing, GlobalSIP 2013
CountryUnited States
CityAustin, TX
Period13/12/313/12/5

ASJC Scopus subject areas

  • Information Systems
  • Signal Processing

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