Segment-parallel predictor for FPGA-based hardware compressor and decompressor of floating-point data streams to enhance memory I/O bandwidth

Kentaro Sano, Kazuya Katahira, Satoru Yamamoto

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Citations (Scopus)

Abstract

This paper presents segment-parallel prediction for high-throughput compression and decompression of floating-point data streams on an FPGA-based LBM accelerator. In order to enhance the actual memory I/O bandwidth of the accelerator, we focus on the prediction-based compression of floating-point data streams. Although hardware implementation is essential to high-throughput compression, the feedback loop in the decompressor is a bottleneck due to sequential predictions necessary for bit reconstruction. We introduce a segment-parallel approach to the 1D polynomial predictor to achieve the required throughput for decompression. We evaluate the compression ratio of the segment-parallel cubic prediction with various encoders of prediction difference.

Original languageEnglish
Title of host publicationProceedings - Data Compression Conference, DCC 2010
Pages416-425
Number of pages10
DOIs
Publication statusPublished - 2010 May 31
EventData Compression Conference, DCC 2010 - Snowbird, UT, United States
Duration: 2010 Mar 242010 Mar 26

Publication series

NameData Compression Conference Proceedings
ISSN (Print)1068-0314

Other

OtherData Compression Conference, DCC 2010
CountryUnited States
CitySnowbird, UT
Period10/3/2410/3/26

ASJC Scopus subject areas

  • Computer Networks and Communications

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    Sano, K., Katahira, K., & Yamamoto, S. (2010). Segment-parallel predictor for FPGA-based hardware compressor and decompressor of floating-point data streams to enhance memory I/O bandwidth. In Proceedings - Data Compression Conference, DCC 2010 (pp. 416-425). [5453487] (Data Compression Conference Proceedings). https://doi.org/10.1109/DCC.2010.44