We established a scaling theory for double-gate SOI MOSFET's, which gives a guidance for the device design (silicon thickness tsi; gate oxide thickness tox) so that maintaining a subthreshold factor for a given gate length LG. According to our theory, a device can be designed with a gate length of less than 0.1 μm while maintaining the ideal subthreshold factor, which is verified numerically with a two-dimensional device simulator.
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering