Scalable transformer model based on ladder topological equivalent circuit for Si RFICs

Nobuhiro Shiramizu, Toru Masuda, Takahiro Nakamura, Katsuyoshi Washio

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

Scalable modeling methodology of on-chip spiral interleaved transformer is proposed. The novel equivalent circuit based on ladder topology is composed of lumped elements and their parameters are completely derived from the physical structure. The circuit topology enables to express the inductive and capacitive coupling effect between half turn segmented wires accurately. The circuit also contributes to obtain the scalability related to wire width/space, length, and diameter. In this model, coupling capacitance between adjacent wires is given by considering parallel paths through oxide layer and Si substrate. The model simulation result matched the measurement result of a fabricated transformer TEG with the error less than 5% for wide frequency range upto quasi-millimeter wave band.

Original languageEnglish
Title of host publication2010 10th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, SiRF 2010 - Digest of Papers
Pages12-15
Number of pages4
DOIs
Publication statusPublished - 2010 Apr 23
Externally publishedYes
Event2010 10th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, SiRF 2010 - New Orleans, LA, United States
Duration: 2010 Jan 112010 Jan 13

Other

Other2010 10th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, SiRF 2010
Country/TerritoryUnited States
CityNew Orleans, LA
Period10/1/1110/1/13

Keywords

  • Coupling effect
  • Ladder topology
  • On-chip transformer
  • Scalable model

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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