Scalable serial-configuration scheme for MTJ/MOS-hybrid variation-resilient VLSI system

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

A new circuit-characteristic configuration scheme of a nonvolatile logic circuit, where magnetic tunnel junction (MTJ) devices are combined with MOS transistors, is proposed for realizing process, voltage, temperature (PVT)-variation-aware VLSI systems. Faulty logic-function results due to PVT variation are detected by monitoring input-output characteristics of each logic-circuit cell, and adjusted by configuring resistance values of MTJ devices embedded into each logic-circuit cell. The resistance values of MTJ devices are programmed in bit-serial manner by the proposed scheme, which can suppress not only area overhead due to incorporating configuration function but also the number of control signals from peripheral circuitry. It results in adding the configuration capability with compact and scalable implementation.

Original languageEnglish
Title of host publication2012 IEEE 10th International New Circuits and Systems Conference, NEWCAS 2012
Pages97-100
Number of pages4
DOIs
Publication statusPublished - 2012
Event2012 IEEE 10th International New Circuits and Systems Conference, NEWCAS 2012 - Montreal, QC, Canada
Duration: 2012 Jun 172012 Jun 20

Publication series

Name2012 IEEE 10th International New Circuits and Systems Conference, NEWCAS 2012

Other

Other2012 IEEE 10th International New Circuits and Systems Conference, NEWCAS 2012
CountryCanada
CityMontreal, QC
Period12/6/1712/6/20

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Control and Systems Engineering

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