Scalable Hardware Architecture for Invertible Logic with Sparse Hamiltonian Matrices

Naoya Onizawa; Akira Tamakoshi; Takahiro Hanyu

doi:10.1109/SiPS52927.2021.00047

Scalable Hardware Architecture for Invertible Logic with Sparse Hamiltonian Matrices

Naoya Onizawa, Akira Tamakoshi, Takahiro Hanyu

Systems & Software Division

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

We introduce a scalable hardware architecture for large-scale invertible logic. Invertible logic has been recently presented that can realize bidirectional computing probabilis-tically based on Hamiltonians with a small number of non-zero elements. In order to store and compute the Hamiltonians efficiently in hardware, a sparse matrix representation of PTELL (partitioned and transposed ELLPACK) is proposed. A memory size of PTELL can be smaller than that of a conventional ELL by reducing the number of paddings while parallel reading of non-zero values are realized for high-throughput operations. As a result, the proposed scalable invertible-logic hardware based on PTELL is designed on Xilinx KC705 FPGA board, which achieves two orders of magnitude faster than an 8-core CPU implementation.

Original language	English
Title of host publication	Proceedings - 2021 IEEE Workshop on Signal Processing Systems, SiPS 2021
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	1-6
Number of pages	6
ISBN (Electronic)	9781665401449
DOIs	https://doi.org/10.1109/SiPS52927.2021.00047
Publication status	Published - 2021
Event	2021 IEEE Workshop on Signal Processing Systems, SiPS 2021 - Coimbra, Portugal Duration: 2021 Oct 19 → 2021 Oct 21

Publication series

Name	IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation
Volume	2021-October
ISSN (Print)	1520-6130

Conference

Conference	2021 IEEE Workshop on Signal Processing Systems, SiPS 2021
Country/Territory	Portugal
City	Coimbra
Period	21/10/19 → 21/10/21

Keywords

Bidirectional computing
Boltzmann machine
Sparse matrix
Stochastic computing

ASJC Scopus subject areas

Electrical and Electronic Engineering
Signal Processing
Applied Mathematics
Hardware and Architecture

Access to Document

10.1109/SiPS52927.2021.00047

Cite this

Onizawa, N., Tamakoshi, A., & Hanyu, T. (2021). Scalable Hardware Architecture for Invertible Logic with Sparse Hamiltonian Matrices. In Proceedings - 2021 IEEE Workshop on Signal Processing Systems, SiPS 2021 (pp. 1-6). (IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation; Vol. 2021-October). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/SiPS52927.2021.00047

Scalable Hardware Architecture for Invertible Logic with Sparse Hamiltonian Matrices. / Onizawa, Naoya; Tamakoshi, Akira; Hanyu, Takahiro.

Proceedings - 2021 IEEE Workshop on Signal Processing Systems, SiPS 2021. Institute of Electrical and Electronics Engineers Inc., 2021. p. 1-6 (IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation; Vol. 2021-October).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Onizawa, N, Tamakoshi, A & Hanyu, T 2021, Scalable Hardware Architecture for Invertible Logic with Sparse Hamiltonian Matrices. in Proceedings - 2021 IEEE Workshop on Signal Processing Systems, SiPS 2021. IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation, vol. 2021-October, Institute of Electrical and Electronics Engineers Inc., pp. 1-6, 2021 IEEE Workshop on Signal Processing Systems, SiPS 2021, Coimbra, Portugal, 21/10/19. https://doi.org/10.1109/SiPS52927.2021.00047

Onizawa N, Tamakoshi A, Hanyu T. Scalable Hardware Architecture for Invertible Logic with Sparse Hamiltonian Matrices. In Proceedings - 2021 IEEE Workshop on Signal Processing Systems, SiPS 2021. Institute of Electrical and Electronics Engineers Inc. 2021. p. 1-6. (IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation). doi: 10.1109/SiPS52927.2021.00047

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abstract = "We introduce a scalable hardware architecture for large-scale invertible logic. Invertible logic has been recently presented that can realize bidirectional computing probabilis-tically based on Hamiltonians with a small number of non-zero elements. In order to store and compute the Hamiltonians efficiently in hardware, a sparse matrix representation of PTELL (partitioned and transposed ELLPACK) is proposed. A memory size of PTELL can be smaller than that of a conventional ELL by reducing the number of paddings while parallel reading of non-zero values are realized for high-throughput operations. As a result, the proposed scalable invertible-logic hardware based on PTELL is designed on Xilinx KC705 FPGA board, which achieves two orders of magnitude faster than an 8-core CPU implementation. ",

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Scalable Hardware Architecture for Invertible Logic with Sparse Hamiltonian Matrices

Abstract

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Keywords

ASJC Scopus subject areas

Access to Document

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