Scalability study on a capacitorless 1T-DRAM: From single-gate PD-SOI to double-gate FinDRAM

T. Tanaka, E. Yoshida, T. Miyashita

Research output: Contribution to journalConference articlepeer-review

52 Citations (Scopus)

Abstract

This paper describes both operation principle and scalability of a capacitor-less 1T-DRAM, and proposes a new concept about extending the use of 1T-DRAM to gate lengths of less than 50 nm. Superior characteristics such as long retention time and large sense margin even for gate lengths around 50 nm can be obtained with a double-gate fully depleted FinFET DRAM. Considering capacity, speed, power, and structural complexity of embedded memory, the capacitor-less 1T-DRAM has the possibility of playing the leading part among other memories.

Original languageEnglish
Pages (from-to)919-922
Number of pages4
JournalTechnical Digest - International Electron Devices Meeting, IEDM
Publication statusPublished - 2004
Externally publishedYes
EventIEEE International Electron Devices Meeting, 2004 IEDM - San Francisco, CA, United States
Duration: 2004 Dec 132004 Dec 15

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry

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