Scalability of vertical MOSFETs in sub-10nm generation and its mechanism

Tetsuo Endoh, Yuto Norifusa

Research output: Contribution to journalArticlepeer-review

18 Citations (Scopus)


In this paper, the device performances of sub-10nm Vertical MOSFETs are investigated. One of the drawbacks of conventional planar MOSFETs is that in the sub-10nm generation, its cutoff leakage current increases due to the short channel effects, but even more, its driving current decreases due to the quantum mechanical confinement effects such as the sub-band effect and the depletion of the inversion layer. It is shown for the first time that by downscaling the silicon pillar diameter from 20 nm to 4 nm, the Vertical MOSFET increases its driving current per footprint to about 2 times and suppresses its total cutoff leakage current per footprint to less than 1/60 at the same time. Moreover, the mechanisms of these improvements of Vertical MOSFET performances are clarified. The results of this work show that Vertical MOSFETs can overcome the drawbacks of conventional planar MOSFETs and achieve the high device performance through the sub-10 nm generation.

Original languageEnglish
Pages (from-to)594-597
Number of pages4
JournalIEICE Transactions on Electronics
Issue number5
Publication statusPublished - 2009


  • Current density
  • Cutoff leakage current
  • Driving current
  • Sub-10nm
  • Vertical MOSFETs

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering


Dive into the research topics of 'Scalability of vertical MOSFETs in sub-10nm generation and its mechanism'. Together they form a unique fingerprint.

Cite this