We demonstrate for the first time the scalability of NiSi and Ni 3Si FUSI gate processes down to 30 nm gate lengths, with linewidth independent phase and Vt control. We show that 1-step FUSI is inadequate for NiSi FUSI gates, because it results in incomplete silicidation at low thermal budgets or in a linewidth dependent Ni suicide phase -inducing Vt shifts- at higher thermal budgets. We show that Vt and WF shifts are larger on high-K (HfO2 (250 mV) or HfSiON (330mV)) than on SiON (110mV) and report Fermi level unpinning for Ni-rich FUSI on high-K. In contrast, we demonstrate the scalability of Ni3Si FUSI, with no phase control issues, and report HfSiON Ni3Si FUSI PMOS devices with Vt= -0.33 V. Lastly, we show that, for NiSi, phase control down to narrow gate lengths can be obtained with a 2-step FUSI process.
|Number of pages||2|
|Journal||Digest of Technical Papers - Symposium on VLSI Technology|
|Publication status||Published - 2005 Dec 1|
|Event||2005 Symposium on VLSI Technology - Kyoto, Japan|
Duration: 2005 Jun 14 → 2005 Jun 14
ASJC Scopus subject areas
- Electrical and Electronic Engineering