Scalability analysis of deeply pipelined tsunami simulation with multiple FPGAs

Antoniette Mondigo, Tomohiro Ueno, Kentaro Sano, Hiroyuki Takizawa

Research output: Contribution to journalArticlepeer-review

5 Citations (Scopus)

Abstract

Since the hardware resource of a single FPGA is limited, one idea to scale the performance of FPGA-based HPC applications is to expand the design space with multiple FPGAs. This paper presents a scalable architecture of a deeply pipelined stream computing platform, where available parallelism and inter-FPGA link characteristics are investigated to achieve a scaled performance. For a practical exploration of this vast design space, a performance model is presented and verified with the evaluation of a tsunami simulation application implemented on Intel Arria 10 FPGAs. Finally, scalability analysis is performed, where speedup is achieved when increasing the computing pipeline over multiple FPGAs while maintaining the problem size of computation. Performance is scaled with multiple FPGAs; however, performance degradation occurs with insufficient available bandwidth and large pipeline overhead brought by inadequate data stream size. Tsunami simulation results show that the highest scaled performance for 8 cascaded Arria 10 FPGAs is achieved with a single pipeline of 5 stream processing elements (SPEs), which obtained a scaled performance of 2.5 TFlops and a parallel efficiency of 98%, indicating the strong scalability of the multi-FPGA stream computing platform.

Original languageEnglish
Pages (from-to)1029-1036
Number of pages8
JournalIEICE Transactions on Information and Systems
VolumeE102D
Issue number5
DOIs
Publication statusPublished - 2019 May

Keywords

  • High-performance computing
  • Multiple FPGAs
  • Scalability
  • Stream computing
  • Tsunami simulation

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Computer Vision and Pattern Recognition
  • Electrical and Electronic Engineering
  • Artificial Intelligence

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