Rigorous design of 22-nm node 4-terminal SOI FinFETs for reliable low standby power operation with semi-empirical parameters

Seongjae Cho, Shinichi O'uchi, Kazuhiko Endo, Sang Wan Kim, Younghwan Son, In Man Kang, Meishoku Masahara, James S. Harris, Byung Gook Park

Research output: Contribution to journalArticlepeer-review

6 Citations (Scopus)

Abstract

In this work, reliable methodology for device design is presented. Based on this method, the underlap length has been optimized for minimizing the gateinduced drain leakage (GIDL) in a 22-nm node 4-terminal (4-T) silicon-on-insulator (SOI) fin-shaped field effect transistor (FinFET) by TCAD simulation. In order to examine the effects of underlap length on GIDL more realistically, doping profile of the source and drain (S/D) junctions, carrier lifetimes, and the parameters for a band-to-band tunneling (BTBT) model have been experimentally extracted from the devices of 90-nm channel length as well as pnjunction test element groups (TEGs). It was confirmed that the underlap length should be near 15 nm to suppress GIDL effectively for reliable low standby power (LSTP) operation.

Original languageEnglish
Pages (from-to)265-275
Number of pages11
JournalJournal of Semiconductor Technology and Science
Volume10
Issue number4
DOIs
Publication statusPublished - 2010 Dec
Externally publishedYes

Keywords

  • Bandto-band tunneling (BTBT)
  • Carrier lifetime
  • Device design
  • Fin-shaped field-effect transistor (FinFET)
  • Gate-induced drain leakage (GIDL)
  • TCAD simulation
  • Underlap length

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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