Review of STT-MRAM circuit design strategies, and a 40-nm 1T-1MTJ 128Mb STT-MRAM design practice

Hiroki Koike, Takaho Tanigawa, Toshinari Watanabe, Takashi Nasuno, Yasuo Noguchi, Mitsuo Yasuhira, Toru Yoshiduka, Yitao Ma, Hiroaki Honjo, Koichi Nishioka, Sadahiko Miura, Hirofumi Inoue, Shoji Ikeda, Tetsuo Endoh

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

STT-MRAM is now an essential component for future low power consumption electronics. Recently, a number of STT-MRAM developments have been successively disclosed by major LSI vendors [1] -[9], and some of them announced that risk mass-production of STT-MRAM had started. This invited paper reviews, in this opportunity, STT-MRAM circuit design strategies, which cover memory cell design, sense amplifier (S/A) and reference generator (Refgen), and array architecture. Furthermore, as one example of STT-MRAM design, a 128Mb STT-MRAM chip using 40-nm standard CMOS and 3X-nm MTJ technology will be presented [10].

Original languageEnglish
Title of host publication2020 IEEE 31st Magnetic Recording Conference, TMRC 2020
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728161778
DOIs
Publication statusPublished - 2020 Aug 17
Event31st IEEE Magnetic Recording Conference, TMRC 2020 - Berkeley, United States
Duration: 2020 Aug 172020 Aug 20

Publication series

Name2020 IEEE 31st Magnetic Recording Conference, TMRC 2020

Conference

Conference31st IEEE Magnetic Recording Conference, TMRC 2020
Country/TerritoryUnited States
CityBerkeley
Period20/8/1720/8/20

ASJC Scopus subject areas

  • Media Technology

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