Residue arithmetic based multiple-valued VLSI image processor

Makoto Honda, Michitaka Kameyama, Tatsuo Higuchi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

An ultra-high-performance VLSI image processor based on a multivalued residue arithmetic circuit is proposed for robot vision. Data communication between the mod mi arithmetic units is not necessary in the residue arithmetic system, so that multiple mod mi arithmetic units can be on different chips. Therefore, a number of mod mi multiplier adders can be implemented on a single VLSI chip based on the modulus-slice concept. Each mod mi arithmetic unit can be effectively implemented in parallel using the concept of pseudoprimitive root and multivalued current-mode circuit technology. Thus, the use of parallelism throughout makes the performance very high in comparison with the ordinary binary implementation.

Original languageEnglish
Title of host publicationProceedings of The International Symposium on Multiple-Valued Logic
PublisherPubl by IEEE
Pages330-336
Number of pages7
ISBN (Print)0818626801
Publication statusPublished - 1992 May 1
EventProceedings of the 22nd International Symposium on Multiple-Valued Logic - Sendai, Jpn
Duration: 1992 May 271992 May 29

Publication series

NameProceedings of The International Symposium on Multiple-Valued Logic
ISSN (Print)0195-623X

Other

OtherProceedings of the 22nd International Symposium on Multiple-Valued Logic
CitySendai, Jpn
Period92/5/2792/5/29

ASJC Scopus subject areas

  • Computer Science(all)
  • Mathematics(all)

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