Integration of III-V channel MISFETs on the Si platform expectedly improves the performance and reduces the power consumption of CMOS devices with sub-10 nm gate lengths. Issues relating to the dielectrics/III-V interfaces are explored in this paper. A wide variety of interface structures were prepared by employing MOCVD-grown epitaxial wafers, surface reconstruction control in MBE, wet/dry surface pretreatments, and deposition of dielectrics (Al 2O3, HfO2) by ALD or electron-beam evaporation. Relationships between the structures of the interfaces and the MIS properties are discussed, with particular attention to the effects of the cation composition (Al, Ga, In) in the semiconductor bulk and at the interface, anion control at the interface (sulfidation, nitridation), and the surface orientation [(100) versus (111)]. Recent developments in III-V-on-insulator wafer technology are also reported.