Reconfigured-wafer-to-wafer 3-D integration using parallel self-assembly of chips with cu-snAg microbumps and a nonconductive film

Takafumi Fukushima, Jichoru Be, Hisashi Kino, Chisato Nagai, Mariappan Murugesan, Hideto Hashiguchi, Kanuku Ri, Tetsu Tanaka, Mitsumasa Koyanagi

Research output: Contribution to journalArticle

36 Citations (Scopus)

Abstract

A new 3-D integration concept based on reconfigured wafer-to-wafer stacking is proposed. Using reconfigured wafer-to-wafer 3-D integration, many known-good dies (KGDs) can be simultaneously and precisely self-assembled by water surface tension onto a carrier wafer, which is called a reconfigured wafer. In addition, the KGDs on the reconfigured wafer can be transferred and bonded to another target wafer at the wafer level. The alignment accuracy is within 1 μm when 3 × 3-, 5 × 5-, 4 × 9,- or 10 × 10-mm 2 chips are employed. To 3-D stack many KGDs in a batch process, we developed and employed a self-assembly multichip bonder. KGDs with 20-μ m-pitch Cu-SnAg microbumps covered with a nonconductive film as a preapplied underfill material on their top surface were self-assembled right-side up, and then transferred to the corresponding target interposer wafer upside down. The resulting daisy chain with 500 Cu-SnAg microbumps exhibited ohmic contacts, and the resistance of ∼40 mΩ/bump was sufficiently low for 3-D large-scale integration application.

Original languageEnglish
Article number6698357
Pages (from-to)533-539
Number of pages7
JournalIEEE Transactions on Electron Devices
Volume61
Issue number2
DOIs
Publication statusPublished - 2014 Jan 1

Keywords

  • 3-D integration
  • Alignment
  • Microbump
  • Self-assembly
  • Wafer-level processing
  • Water surface tension

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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