Reconfigurable synchronized dataflow processor

Hiroshi Sasaki, Hitoshi Maruyama, Hideaki Tsukioka, Nobuyoshi Shoji, Hiroaki Kobayashi, Tadao Nakamura

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper describes the design and implementation of a reconfigurable synchronized dataflow processor (RSDP). The RSDP can configure its hardware to directly represent dataflow graphs (DFGs) of applications. Data are processed while they flow along application-specific datapaths in the RSDP. We have designed three DFGs for benchmarking and evaluated their performance on an RSDP board. The results show that the RSDP running at relatively lower frequency can achieve a competitive performance with a general-purpose processor.

Original languageEnglish
Title of host publicationProceedings of the 2000 Asia and South Pacific Design Automation Conference, ASP-DAC 2000
Pages27-28
Number of pages2
DOIs
Publication statusPublished - 2000 Dec 1
Event2000 Asia and South Pacific Design Automation Conference, ASP-DAC 2000 - Yokohama, Japan
Duration: 2000 Jan 252000 Jan 28

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Other

Other2000 Asia and South Pacific Design Automation Conference, ASP-DAC 2000
CountryJapan
CityYokohama
Period00/1/2500/1/28

ASJC Scopus subject areas

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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