Reconfigurable parallel VLSI processor for dynamic control of intelligent robots

Y. Fujioka, M. Kameyama, N. Tomabechi

Research output: Contribution to journalArticlepeer-review

7 Citations (Scopus)

Abstract

In the sensor feedback control of intelligent robots, the delay time must be reduced for a large number of multiply-additions. To reduce the delay time for multi-operand multiply-additions, the architecture of the reconfigurable parallel processor is proposed. In each PE, a switch circuit (SC) is used to change the connection between multipliers and adders. By changing the switch elements in the SC using the very-long-instruction-word (VLIW) control method, the multiply-adders having desired numbers of multipliers can be reconfigured every clock cycle. Since the data transfer is performed by the direct connection between multipliers and adders, the overhead for data transfer is greatly reduced. In addition, the utilised ratio of the multipliers and the adders is increased. The chip evaluation based on 0.8 μm CMOS design rule shows that the delay time for dynamic control of a seven-degrees-of-freedom (DOF) redundant robot manipulator becomes about 10 μs which is about 7.7 times faster than that of a parallel-processor approach using conventional digital signal processors (DSPs).

Original languageEnglish
Pages (from-to)23-29
Number of pages7
JournalIEE Proceedings: Computers and Digital Techniques
Volume143
Issue number1
DOIs
Publication statusPublished - 1996 Jan 1

Keywords

  • Multi-operand multiply-additions
  • Parallel VLSI processor
  • Reconfiguration
  • Robot electronics systems
  • Small delay time

ASJC Scopus subject areas

  • Theoretical Computer Science
  • Hardware and Architecture
  • Computational Theory and Mathematics

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