Realization of 0.1 μm Buried-Channel PMOSFETs by device restructuring using Tilted Well Implantation technology

T. Tanaka, Y. Momiyama, K. Goto, Y. Sambonsugi, M. Deura, T. Sugii

Research output: Contribution to journalConference articlepeer-review

4 Citations (Scopus)

Abstract

Device restructuring by Tilted Well Implantation (TWI) was proposed for highly cost effective system LSIs. We demonstrated a 0.1 μm Buried-Channel (BC)-PMOSFET with a superior Ion/Ioff ratio, little threshold voltage (Vth) rolloff, and a low Vth using the TWI.

Original languageEnglish
Pages (from-to)109-110
Number of pages2
JournalDigest of Technical Papers - Symposium on VLSI Technology
Publication statusPublished - 1999 Dec 1
Externally publishedYes
EventProceedings of the 1999 Symposium on VLSI Technology - Kyoto, Jpn
Duration: 1999 Jun 141999 Jun 16

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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