Realization of 0.1 μm Buried-Channel PMOSFETs by device restructuring using Tilted Well Implantation technology

T. Tanaka; Y. Momiyama; K. Goto; Y. Sambonsugi; M. Deura; T. Sugii

Realization of 0.1 μm Buried-Channel PMOSFETs by device restructuring using Tilted Well Implantation technology

T. Tanaka, Y. Momiyama, K. Goto, Y. Sambonsugi, M. Deura, T. Sugii

Research output: Contribution to journal › Conference article › peer-review

Abstract

Device restructuring by Tilted Well Implantation (TWI) was proposed for highly cost effective system LSIs. We demonstrated a 0.1 μm Buried-Channel (BC)-PMOSFET with a superior Ion/Ioff ratio, little threshold voltage (Vth) rolloff, and a low Vth using the TWI.

Original language	English
Pages (from-to)	109-110
Number of pages	2
Journal	Digest of Technical Papers - Symposium on VLSI Technology
Publication status	Published - 1999 Dec 1
Externally published	Yes
Event	Proceedings of the 1999 Symposium on VLSI Technology - Kyoto, Jpn Duration: 1999 Jun 14 → 1999 Jun 16

ASJC Scopus subject areas

Electrical and Electronic Engineering

Cite this

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title = "Realization of 0.1 μm Buried-Channel PMOSFETs by device restructuring using Tilted Well Implantation technology",

abstract = "Device restructuring by Tilted Well Implantation (TWI) was proposed for highly cost effective system LSIs. We demonstrated a 0.1 μm Buried-Channel (BC)-PMOSFET with a superior Ion/Ioff ratio, little threshold voltage (Vth) rolloff, and a low Vth using the TWI.",

author = "T. Tanaka and Y. Momiyama and K. Goto and Y. Sambonsugi and M. Deura and T. Sugii",

year = "1999",

month = dec,

day = "1",

language = "English",

pages = "109--110",

journal = "Digest of Technical Papers - Symposium on VLSI Technology",

issn = "0743-1562",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "Proceedings of the 1999 Symposium on VLSI Technology ; Conference date: 14-06-1999 Through 16-06-1999",

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TY - JOUR

T1 - Realization of 0.1 μm Buried-Channel PMOSFETs by device restructuring using Tilted Well Implantation technology

AU - Tanaka, T.

AU - Momiyama, Y.

AU - Goto, K.

AU - Sambonsugi, Y.

AU - Deura, M.

AU - Sugii, T.

PY - 1999/12/1

Y1 - 1999/12/1

N2 - Device restructuring by Tilted Well Implantation (TWI) was proposed for highly cost effective system LSIs. We demonstrated a 0.1 μm Buried-Channel (BC)-PMOSFET with a superior Ion/Ioff ratio, little threshold voltage (Vth) rolloff, and a low Vth using the TWI.

AB - Device restructuring by Tilted Well Implantation (TWI) was proposed for highly cost effective system LSIs. We demonstrated a 0.1 μm Buried-Channel (BC)-PMOSFET with a superior Ion/Ioff ratio, little threshold voltage (Vth) rolloff, and a low Vth using the TWI.

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M3 - Conference article

AN - SCOPUS:0033280029

SP - 109

EP - 110

JO - Digest of Technical Papers - Symposium on VLSI Technology

JF - Digest of Technical Papers - Symposium on VLSI Technology

SN - 0743-1562

T2 - Proceedings of the 1999 Symposium on VLSI Technology

Y2 - 14 June 1999 through 16 June 1999

ER -

Realization of 0.1 μm Buried-Channel PMOSFETs by device restructuring using Tilted Well Implantation technology

Abstract

ASJC Scopus subject areas

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