## Abstract

This paper presents a hardware algorithm for a real/complex reconfigurable arithmetic unit, which can change its structure for three different arithmetic, modes in real time. The three modes realize (i) a single-precision complex-number multiplication, (ii) a double-precision real-number multiplication, and (iii) a pair of single-precision real-number four-operand multiply-add operations, respectively. We discuss the reconfiguration of hardware structure on the basis of the transformation of the number system used in each arithmetic mode. The designed arithmetic unit can perform high-speed real/complex arithmetic computations based on binary-tree addition scheme, and also exhibits highly regular structure suited for VLSI implementation.

Original language | English |
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Pages | 200-207 |

Number of pages | 8 |

Publication status | Published - 1997 Jan 1 |

Event | Proceedings of the 1997 13th IEEE Symposium on Computer Arithmetic - Asilomar, CA, USA Duration: 1997 Jul 6 → 1997 Jul 9 |

### Other

Other | Proceedings of the 1997 13th IEEE Symposium on Computer Arithmetic |
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City | Asilomar, CA, USA |

Period | 97/7/6 → 97/7/9 |

## ASJC Scopus subject areas

- Software
- Theoretical Computer Science
- Hardware and Architecture