A very large-scale integration (VLSI) recognition system equipped with an on-chip learning capability has been developed for real-time processing applications. This system can work in two functional modes of operation: adaptive K-means learning mode and recognition mode. In the adaptive K-means learning mode, the variance ratio criterion (VRC) has been employed to evaluate the quality of K-means classification results, and the evaluation algorithm has been implemented on the chip. As a result, it has become possible for the system to autonomously determine the optimum number of clusters (K). In the recognition mode, the nearest-neighbor search algorithm is very efficiently carried out by the fully parallel architecture employed in the chip. In both modes of operation, many hardware resources are shared and the functionality is flexibly altered by the system controller designed as a finite-state machine (FSM). The chip is implemented on Altera Cyclone II FPGA with 46K logic cells. Its operating clock is 25MHz and the processing times for adaptive learning and recognition with 256 64-dimension feature vectors are about 0.42 ms and 4 s, respectively. Both adaptive K-means learning and recognition functions have been verified by experiments using the image data from the COIL-100 (Columbia University Object Image Library) database.
ASJC Scopus subject areas
- Physics and Astronomy(all)