Ray tracing hardware system using plane-sphere intersections

Yoshiyuki Kaeriyama, Daichi Zaitsu, Kazuhiko Komatsu, Kenichi Suzuki, Tadao Nakamura, Nobuyuki Ohba

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Ray tracing is a global illumination based rendering method widely used in computer graphics. Although it generates photo-realistic images, it requires a large number of computations. In ray tracing, the ray-object intersection test is one of the dominant factors for the processing speed. To accelerate the intersection test, we propose a new method based on a plane-sphere intersection algorithm, and show a hardware system using an FPGA. The computations used in the method are highly pipelined and parallelized by optimizing the balance between the computation speed and the memory data bandwidth. As a result, the prototype makes full use of 512 DSP cores built in Xilinx Vertex-4 SX FPGA, and the average utilization of the DSP cores is close to 90%. The simulation results show that the proposed system running at 160MHz performs the intersection test a few hundred times faster than a commodity PC with a 3.4GHz Pentium 4.

Original languageEnglish
Title of host publicationProceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL
Pages315-320
Number of pages6
DOIs
Publication statusPublished - 2006 Dec 1
Event2006 International Conference on Field Programmable Logic and Applications, FPL - Madrid, Spain
Duration: 2006 Aug 282006 Aug 30

Publication series

NameProceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL

Other

Other2006 International Conference on Field Programmable Logic and Applications, FPL
Country/TerritorySpain
CityMadrid
Period06/8/2806/8/30

ASJC Scopus subject areas

  • Computational Theory and Mathematics
  • Electrical and Electronic Engineering

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