QUATERNARY GATE ARRAY FOR PATTERN MATCHING AND ITS APPLICATION TO KNOWLEDGE INFORMATION PROCESSING SYSTEM.

Takahiro Hanyu, Michitaka Kameyama, Tatsuo Higuchi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

A quaternary gate array for high-speed pattern matching, based on totally parallel structure, is presented. This gate array can be used in real-time applications when the rules are fixed. The chip can be implemented by a standard NMOS process with multiple ion implants. The rules can be programmed by setting the threshold of the transistor to one of the four states. It is demonstrated that the chip area for pattern matching can be reduced by 30% compared with the corresponding binary gate array.

Original languageEnglish
Title of host publicationProceedings of The International Symposium on Multiple-Valued Logic
PublisherIEEE
Pages181-187
Number of pages7
ISBN (Print)0818607750
Publication statusPublished - 1987 Jan 1

Publication series

NameProceedings of The International Symposium on Multiple-Valued Logic
ISSN (Print)0195-623X

ASJC Scopus subject areas

  • Computer Science(all)
  • Mathematics(all)

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